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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 15:26:33 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 15:26:33 +0100 |
| commit | 947492867238d47c014189a0de2d49f3e5d9bbbc (patch) | |
| tree | 2bc5c98f48796e357ba806dcd773da973209565a /techlibs/xilinx/tests | |
| parent | 4a0b3a5423175eed7f1de9e975ee1fb20a2eb3ae (diff) | |
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/tests')
| -rw-r--r-- | techlibs/xilinx/tests/bram1.sh | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/tests/bram1_tb.v | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh index f233be9f..15c4034a 100644 --- a/techlibs/xilinx/tests/bram1.sh +++ b/techlibs/xilinx/tests/bram1.sh @@ -1,5 +1,7 @@ #!/bin/bash +set -e + use_xsim=false unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v index c14cf6e3..dbefdb6e 100644 --- a/techlibs/xilinx/tests/bram1_tb.v +++ b/techlibs/xilinx/tests/bram1_tb.v @@ -70,7 +70,7 @@ module bram1_tb #( expected_rd[j] = RD_DATA[j]; end - $display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR"); + $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR"); if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end end end |