Renamed techlibs/xilinx7 to techlibs/xilinx

4 files changed, 0 insertions, 104 deletions

diff --git a/techlibs/xilinx7/example_mojo_counter/README b/techlibs/xilinx7/example_mojo_counter/README
deleted file mode 100644
index 690a9d84..00000000
--- a/techlibs/xilinx7/example_mojo_counter/README
+++ /dev/null
@@ -1,10 +0,0 @@
-
-This is a simple example for Yosys synthesis targeting the Mojo FPGA
-development board [1, 2]. Simple script for xst-based synthesis (incl.
-generation of reference edif files) and uploading to the board can be
-found here [3].
-
-[1] http://embeddedmicro.com/tutorials/mojo
-[2] https://www.sparkfun.com/products/11953
-[3] http://svn.clifford.at/handicraft/2013/mojo/
-
diff --git a/techlibs/xilinx7/example_mojo_counter/example.sh b/techlibs/xilinx7/example_mojo_counter/example.sh
deleted file mode 100644
index 87af0ea3..00000000
--- a/techlibs/xilinx7/example_mojo_counter/example.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
-XILINX_PART=xc6slx9-2-tqg144
-
-../../../yosys - << EOT
-# read design
-read_verilog example.v
-
-# high-level synthesis
-hierarchy -check -top top
-proc; opt; fsm; opt; techmap; opt
-
-# mapping logic to LUTs using Berkeley ABC
-abc -lut 6; opt
-
-# map internal cells to FPGA cells
-techmap -map ../cells.v; opt
-
-# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad BUFGP O:I
-
-# write netlist
-write_edif synth.edif
-EOT
-
-cat > bitgen.ut <<- EOT
-	-w
-	-g DebugBitstream:No
-	-g Binary:no
-	-g CRC:Enable
-	-g Reset_on_err:No
-	-g ConfigRate:2
-	-g ProgPin:PullUp
-	-g TckPin:PullUp
-	-g TdiPin:PullUp
-	-g TdoPin:PullUp
-	-g TmsPin:PullUp
-	-g UnusedPin:PullDown
-	-g UserID:0xFFFFFFFF
-	-g ExtMasterCclk_en:No
-	-g SPI_buswidth:1
-	-g TIMER_CFG:0xFFFF
-	-g multipin_wakeup:No
-	-g StartUpClk:CClk
-	-g DONE_cycle:4
-	-g GTS_cycle:5
-	-g GWE_cycle:6
-	-g LCK_cycle:NoWait
-	-g Security:None
-	-g DonePipe:No
-	-g DriveDone:No
-	-g en_sw_gsr:No
-	-g drive_awake:No
-	-g sw_clk:Startupclk
-	-g sw_gwe_cycle:5
-	-g sw_gts_cycle:4
-EOT
-
-$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
-$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
-$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
-$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
-$XILINX_DIR/bin/lin64/bitgen -f bitgen.ut placed.ncd example.bit constraints.pcf
-
diff --git a/techlibs/xilinx7/example_mojo_counter/example.ucf b/techlibs/xilinx7/example_mojo_counter/example.ucf
deleted file mode 100644
index 591cbe76..00000000
--- a/techlibs/xilinx7/example_mojo_counter/example.ucf
+++ /dev/null
@@ -1,13 +0,0 @@
-NET "clk" TNM_NET = clk;
-TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
-
-NET "clk" LOC = P56;
-
-NET "led_0" LOC = P134;
-NET "led_1" LOC = P133;
-NET "led_2" LOC = P132;
-NET "led_3" LOC = P131;
-NET "led_4" LOC = P127;
-NET "led_5" LOC = P126;
-NET "led_6" LOC = P124;
-NET "led_7" LOC = P123;
diff --git a/techlibs/xilinx7/example_mojo_counter/example.v b/techlibs/xilinx7/example_mojo_counter/example.v
deleted file mode 100644
index 8e79942e..00000000
--- a/techlibs/xilinx7/example_mojo_counter/example.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module top(clk, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-
-input clk;
-output led_7, led_6, led_5, led_4;
-output led_3, led_2, led_1, led_0;
-
-reg [31:0] counter;
-
-always @(posedge clk)
-	counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1;
-
-assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
-
-endmodule