Fixed xilinx bram clock inverted config

1 files changed, 35 insertions, 21 deletions

diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index d9d5391b..89ae07eb 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -51,7 +51,9 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.READ_WIDTH_A(72),
 		.WRITE_WIDTH_B(72),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DOBDO(DO[63:32]),
 		.DOADO(DO[31:0]),
@@ -63,7 +65,7 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.DIPADIP(DIP[3:0]),
 
 		.ADDRARDADDR(A1ADDR_16),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -71,7 +73,7 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.WEA(4'b0),
 
 		.ADDRBWRADDR(B1ADDR_16),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -128,7 +130,9 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.READ_WIDTH_A(36),
 		.WRITE_WIDTH_B(36),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DOBDO(DO[31:16]),
 		.DOADO(DO[15:0]),
@@ -140,7 +144,7 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.DIPADIP(DIP[1:0]),
 
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -148,7 +152,7 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.WEA(2'b0),
 
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -205,14 +209,16 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.WRITE_WIDTH_A(18),
 		.WRITE_WIDTH_B(18),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
 		.DOADO(DO),
 		.DOPADOP(DOP),
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -222,7 +228,7 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.DIBDI(DI),
 		.DIPBDIP(DIP),
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -278,14 +284,16 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.WRITE_WIDTH_A(9),
 		.WRITE_WIDTH_B(9),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
 		.DOADO(DO),
 		.DOPADOP(DOP),
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -295,7 +303,7 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.DIBDI(DI),
 		.DIPBDIP(DIP),
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -351,14 +359,16 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.WRITE_WIDTH_A(4),
 		.WRITE_WIDTH_B(4),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
 		.DOADO(DO),
 		.DOPADOP(DOP),
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -368,7 +378,7 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.DIBDI(DI),
 		.DIPBDIP(DIP),
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -424,14 +434,16 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.WRITE_WIDTH_A(2),
 		.WRITE_WIDTH_B(2),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
 		.DOADO(DO),
 		.DOPADOP(DOP),
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -441,7 +453,7 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.DIBDI(DI),
 		.DIPBDIP(DIP),
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),
@@ -497,14 +509,16 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.WRITE_WIDTH_A(1),
 		.WRITE_WIDTH_B(1),
 		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST")
+		.WRITE_MODE_B("READ_FIRST"),
+		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
+		.IS_CLKBWRCLK_INVERTED(!CLKPOL3)
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
 		.DOADO(DO),
 		.DOPADOP(DOP),
 		.ADDRARDADDR(A1ADDR_14),
-		.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
+		.CLKARDCLK(CLK2),
 		.ENARDEN(|1),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
@@ -514,7 +528,7 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.DIBDI(DI),
 		.DIPBDIP(DIP),
 		.ADDRBWRADDR(B1ADDR_14),
-		.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
+		.CLKBWRCLK(CLK3),
 		.ENBWREN(|1),
 		.REGCEB(|0),
 		.RSTRAMB(|0),