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authorClifford Wolf <clifford@clifford.at>2016-02-01 12:40:32 +0100
committerClifford Wolf <clifford@clifford.at>2016-02-01 12:40:32 +0100
commit17372d8abde0139df4b8df3ebbeb71b222157200 (patch)
treec817af21a34ab38aafd8690fd4fd9f6d8133ec35 /techlibs/xilinx
parent92515535924bcda6b8b9d639764ef8312467db0c (diff)
Added "abc -luts" option, Improved Xilinx logic mapping
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index fbcc9601..6358a266 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -97,7 +97,7 @@ struct SynthXilinxPass : public Pass {
log(" opt -fast\n");
log("\n");
log(" map_luts:\n");
- log(" abc -lut 5:8 [-dff]\n");
+ log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
log(" clean\n");
log("\n");
log(" map_cells:\n");
@@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts"))
{
- Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
+ Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
}