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authorClifford Wolf <clifford@clifford.at>2015-01-06 14:37:50 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 14:37:50 +0100
commit4a0b3a5423175eed7f1de9e975ee1fb20a2eb3ae (patch)
treedbd46dac402b656233bad522637c1410284aa450 /techlibs/xilinx
parent081e1a49f81c298a5c30c4b51241d50ce64f185e (diff)
Various small improvements to synth_xilinx
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc14
1 files changed, 6 insertions, 8 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7b7dbd0f..a0783740 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -74,8 +74,7 @@ struct SynthXilinxPass : public Pass {
log(" techmap -map +/xilinx/brams.v\n");
log("\n");
log(" fine:\n");
- log(" techmap\n");
- log(" opt -fast -full\n");
+ log(" synth -run fine\n");
log("\n");
log(" map_luts:\n");
log(" abc -lut 6\n");
@@ -91,11 +90,11 @@ struct SynthXilinxPass : public Pass {
log("\n");
log(" clkbuf:\n");
log(" select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
- log(" iopadmap -inpad BUFGP O:I @xilinx_clocks\n");
+ log(" iopadmap -bits -inpad BUFGP O:I @xilinx_clocks\n");
log("\n");
log(" iobuf:\n");
log(" select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n");
- log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
+ log(" iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
log("\n");
log(" edif:\n");
log(" write_edif synth.edif\n");
@@ -171,8 +170,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "fine"))
{
- Pass::call(design, "techmap");
- Pass::call(design, "opt -fast -full");
+ Pass::call(design, "synth -run fine");
}
if (check_label(active, run_from, run_to, "map_luts"))
@@ -196,13 +194,13 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "clkbuf"))
{
Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str()));
- Pass::call(design, "iopadmap -inpad BUFGP O:I @xilinx_clocks");
+ Pass::call(design, "iopadmap -bits -inpad BUFGP O:I @xilinx_clocks");
}
if (check_label(active, run_from, run_to, "iobuf"))
{
Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str()));
- Pass::call(design, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
+ Pass::call(design, "iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
}
if (check_label(active, run_from, run_to, "edif"))