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authorClifford Wolf <clifford@clifford.at>2015-01-07 01:28:18 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-07 01:28:18 +0100
commit584c5f3937f11bcfc29eb9b206b941fbc2619b85 (patch)
tree21ceb525f32da9f26816674c8550dc4adf3e1e36 /techlibs/xilinx
parentb26590f8ab2bc77b6209a98240d465af7d3ee266 (diff)
Cleanups in xilinx bram descriptions
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/brams.v64
-rw-r--r--techlibs/xilinx/tests/bram1_tb.v8
2 files changed, 36 insertions, 36 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index cfa598bc..83f2aede 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -209,8 +209,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
- .DOADO(DO[15:0]),
- .DOPADOP(DOP[1:0]),
+ .DOADO(DO),
+ .DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
.ENARDEN(|1),
@@ -219,8 +219,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
.RSTREGARSTREG(|0),
.WEA(2'b0),
- .DIBDI(DI[15:0]),
- .DIPBDIP(DIP[1:0]),
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
@@ -251,8 +251,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 3'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 3'b0};
- wire DIP, DOP;
- wire [7:0] DI, DO;
+ wire [1:0] DIP, DOP;
+ wire [15:0] DI, DO;
wire [8:0] A1DATA_BUF;
reg [8:0] B1DATA_Q;
@@ -268,8 +268,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
- assign A1DATA_BUF = { DOP, DO };
- assign { DIP, DI } = B1DATA;
+ assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("TDP"),
@@ -282,7 +282,7 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
- .DOADO(DO[7:0]),
+ .DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@@ -292,8 +292,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0),
.WEA(2'b0),
- .DIBDI({8'b0, DI}),
- .DIPBDIP({1'b0, DIP}),
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
@@ -324,8 +324,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 2'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 2'b0};
- wire DIP, DOP;
- wire [7:0] DI, DO;
+ wire [1:0] DIP, DOP;
+ wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q;
@@ -341,8 +341,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
- assign A1DATA_BUF = { DOP, DO };
- assign { DIP, DI } = B1DATA;
+ assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("TDP"),
@@ -355,7 +355,7 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
- .DOADO(DO[7:0]),
+ .DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@@ -365,8 +365,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0),
.WEA(2'b0),
- .DIBDI({8'b0, DI}),
- .DIPBDIP({1'b0, DIP}),
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
@@ -397,8 +397,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = {A1ADDR, 1'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 1'b0};
- wire DIP, DOP;
- wire [7:0] DI, DO;
+ wire [1:0] DIP, DOP;
+ wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q;
@@ -414,8 +414,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
- assign A1DATA_BUF = { DOP, DO };
- assign { DIP, DI } = B1DATA;
+ assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("TDP"),
@@ -428,7 +428,7 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
- .DOADO(DO[7:0]),
+ .DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@@ -438,8 +438,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0),
.WEA(2'b0),
- .DIBDI({8'b0, DI}),
- .DIPBDIP({1'b0, DIP}),
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
@@ -470,8 +470,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
wire [13:0] A1ADDR_14 = A1ADDR;
wire [13:0] B1ADDR_14 = B1ADDR;
- wire DIP, DOP;
- wire [7:0] DI, DO;
+ wire [1:0] DIP, DOP;
+ wire [15:0] DI, DO;
wire [3:0] A1DATA_BUF;
reg [3:0] B1DATA_Q;
@@ -487,8 +487,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
assign A1DATA = transparent_cycle ? B1DATA_Q : A1DATA_BUF;
- assign A1DATA_BUF = { DOP, DO };
- assign { DIP, DI } = B1DATA;
+ assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("TDP"),
@@ -501,7 +501,7 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
- .DOADO(DO[7:0]),
+ .DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
@@ -511,8 +511,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
.RSTREGARSTREG(|0),
.WEA(2'b0),
- .DIBDI({8'b0, DI}),
- .DIPBDIP({1'b0, DIP}),
+ .DIBDI(DI),
+ .DIPBDIP(DIP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
.ENBWREN(|1),
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index 6ed04d4a..8f854b74 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -83,16 +83,16 @@ module bram1_tb #(
xorshift64_next;
clk <= 0;
- for (i = 0; i < 256; i = i+1) begin
+ for (i = 0; i < 512; i = i+1) begin
if (DBITS > 64)
WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
else
WR_DATA <= xorshift64_state;
xorshift64_next;
- WR_ADDR <= getaddr(i[7:4]);
+ WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
- RD_ADDR <= getaddr(i[3:0]);
- WR_EN <= ^i;
+ RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
+ WR_EN <= xorshift64_state[55];
xorshift64_next;
#1; clk <= 1;