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authorClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-01 17:09:34 +0100
commit816fe6bbe0ad90f7a696dd208dae6db8139dfd00 (patch)
tree9be22cb0d132ebb6f7c361deb61bb7ebf67f1a8a /techlibs/xilinx
parent6978f3a77baa1220ba0f8a41ca26f5f7bc98dd0a (diff)
Added Xilinx example for Basys3 board
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/cells_sim.v6
-rw-r--r--techlibs/xilinx/example_basys3/README16
-rw-r--r--techlibs/xilinx/example_basys3/example.v21
-rw-r--r--techlibs/xilinx/example_basys3/example.xdc21
-rw-r--r--techlibs/xilinx/example_basys3/run.sh4
-rw-r--r--techlibs/xilinx/example_basys3/run_prog.tcl4
-rw-r--r--techlibs/xilinx/example_basys3/run_vivado.tcl9
-rw-r--r--techlibs/xilinx/example_basys3/run_yosys.ys2
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
9 files changed, 84 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 285d63db..c7f07e40 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -19,7 +19,7 @@ module OBUF(output O, input I);
assign O = I;
endmodule
-module BUFGP(output O, input I);
+module BUFG(output O, input I);
assign O = I;
endmodule
@@ -27,6 +27,10 @@ module OBUFT(output O, input I, T);
assign O = T ? 1'bz : I;
endmodule
+module IOBUF(inout IO, output O, input I, T);
+ assign O = IO, IO = T ? 1'bz : I;
+endmodule
+
module INV(output O, input I);
assign O = !I;
endmodule
diff --git a/techlibs/xilinx/example_basys3/README b/techlibs/xilinx/example_basys3/README
new file mode 100644
index 00000000..85b6eab1
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/README
@@ -0,0 +1,16 @@
+
+A simple example design, based on the Digilent BASYS3 board
+===========================================================
+
+Running Yosys:
+ yosys run_yosys.ys
+
+Running Vivado:
+ vivado -nolog -nojournal -mode batch -source run_vivado.tcl
+
+Programming board:
+ vivado -nolog -nojournal -mode batch -source run_prog.tcl
+
+All of the above:
+ bash run.sh
+
diff --git a/techlibs/xilinx/example_basys3/example.v b/techlibs/xilinx/example_basys3/example.v
new file mode 100644
index 00000000..2b01a22a
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/example.v
@@ -0,0 +1,21 @@
+module example(CLK, LD);
+ input CLK;
+ output [15:0] LD;
+
+ wire clock;
+ reg [15:0] leds;
+
+ BUFG CLK_BUF (.I(CLK), .O(clock));
+ OBUF LD_BUF[15:0] (.I(leds), .O(LD));
+
+ parameter COUNTBITS = 26;
+ reg [COUNTBITS-1:0] counter;
+
+ always @(posedge CLK) begin
+ counter <= counter + 1;
+ if (counter[COUNTBITS-1])
+ leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
+ else
+ leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
+ end
+endmodule
diff --git a/techlibs/xilinx/example_basys3/example.xdc b/techlibs/xilinx/example_basys3/example.xdc
new file mode 100644
index 00000000..c1fd0e92
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/example.xdc
@@ -0,0 +1,21 @@
+
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5 } [get_ports CLK]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3 } [get_ports {LD[9]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3 } [get_ports {LD[10]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3 } [get_ports {LD[11]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3 } [get_ports {LD[12]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3 } [get_ports {LD[13]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1 } [get_ports {LD[14]}]
+set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}]
+
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
+
diff --git a/techlibs/xilinx/example_basys3/run.sh b/techlibs/xilinx/example_basys3/run.sh
new file mode 100644
index 00000000..10f05910
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/run.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+yosys run_yosys.ys
+vivado -nolog -nojournal -mode batch -source run_vivado.tcl
+vivado -nolog -nojournal -mode batch -source run_prog.tcl
diff --git a/techlibs/xilinx/example_basys3/run_prog.tcl b/techlibs/xilinx/example_basys3/run_prog.tcl
new file mode 100644
index 00000000..d711af84
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/run_prog.tcl
@@ -0,0 +1,4 @@
+connect_hw_server
+open_hw_target [lindex [get_hw_targets] 0]
+set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
+program_hw_devices [lindex [get_hw_devices] 0]
diff --git a/techlibs/xilinx/example_basys3/run_vivado.tcl b/techlibs/xilinx/example_basys3/run_vivado.tcl
new file mode 100644
index 00000000..c3b6a610
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/run_vivado.tcl
@@ -0,0 +1,9 @@
+read_xdc example.xdc
+read_edif example.edif
+link_design -part xc7a35tcpg236-1 -top example
+opt_design
+place_design
+route_design
+report_utilization
+report_timing
+write_bitstream -force example.bit
diff --git a/techlibs/xilinx/example_basys3/run_yosys.ys b/techlibs/xilinx/example_basys3/run_yosys.ys
new file mode 100644
index 00000000..4541826d
--- /dev/null
+++ b/techlibs/xilinx/example_basys3/run_yosys.ys
@@ -0,0 +1,2 @@
+read_verilog example.v
+synth_xilinx -edif example.edif -top example
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b3776b3d..caa7e205 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -68,6 +68,7 @@ struct SynthXilinxPass : public Pass {
log("The following commands are executed by this synthesis command:\n");
log("\n");
log(" begin:\n");
+ log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@@ -151,6 +152,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "begin"))
{
+ Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str()));
}