Towards Xilinx bram support

3 files changed, 10 insertions, 6 deletions

diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index aaab8d47..49219c8a 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -13,8 +13,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 	input [71:0] B1DATA;
 	input [7:0] B1EN;
 
-	wire [15:0] A1ADDR_16 = A1ADDR;
-	wire [15:0] B1ADDR_16 = B1ADDR;
+	wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
+	wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
 
 	wire [7:0] DIP, DOP;
 	wire [63:0] DI, DO;
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
index 3a72cce4..fe807ad8 100644
--- a/techlibs/xilinx/tests/bram1.sh
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -22,9 +22,9 @@ for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
 		echo "xvlog --work gold bram1_tb.v bram1.v > gold.txt"
 		echo "xvlog --work gate bram1_tb.v synth.v > gate.txt"
 		echo "xelab -R gold.bram1_tb >> gold.txt"
-		echo "mv testbench.vcd gold.vcd"
+		# echo "mv testbench.vcd gold.vcd"
 		echo "xelab -L unisim -R gate.bram1_tb >> gate.txt"
-		echo "mv testbench.vcd gate.vcd"
+		# echo "mv testbench.vcd gate.vcd"
 		echo "../bram1_cmp <( grep '#OUT#' gold.txt; ) <( grep '#OUT#' gate.txt; )"
 	} > bram1_$id/run.sh
 	{
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index 98e6bafe..c14cf6e3 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -40,10 +40,13 @@ module bram1_tb #(
 	reg [DBITS-1:0] memory [0:2**ABITS-1];
 	reg [DBITS-1:0] expected_rd;
 
+	event error;
+	reg error_ind = 0;
+
 	integer i, j;
 	initial begin
-		$dumpfile("testbench.vcd");
-		$dumpvars(0, bram1_tb);
+		// $dumpfile("testbench.vcd");
+		// $dumpvars(0, bram1_tb);
 		clk <= 0;
 		for (i = 0; i < 256; i = i+1) begin
 			WR_DATA <= i;
@@ -68,6 +71,7 @@ module bram1_tb #(
 			end
 
 			$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
+			if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
 		end
 	end
 endmodule