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authorClifford Wolf <clifford@clifford.at>2015-01-06 23:21:52 +0100
committerClifford Wolf <clifford@clifford.at>2015-01-06 23:21:52 +0100
commitec2eef89fab03beb655f4fe3a16b002d3bf439f7 (patch)
tree3980298c8c40b8bab28a0a67399360c56b6179ee /techlibs/xilinx
parent7cc5192125244d3fd990f3043d619262066ff962 (diff)
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx')
-rw-r--r--techlibs/xilinx/brams.txt26
-rw-r--r--techlibs/xilinx/brams.v4
-rw-r--r--techlibs/xilinx/tests/bram1_tb.v59
3 files changed, 65 insertions, 24 deletions
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt
index 0d039d78..59af1bc5 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/brams.txt
@@ -12,7 +12,7 @@ bram $__XILINX_RAMB36_SDP72
endbram
bram $__XILINX_RAMB18_SDP36
- abits 10
+ abits 9
dbits 36
groups 2
ports 1 1
@@ -24,7 +24,7 @@ bram $__XILINX_RAMB18_SDP36
endbram
bram $__XILINX_RAMB18_TDP18
- abits 11
+ abits 10
dbits 18
groups 2
ports 1 1
@@ -36,7 +36,7 @@ bram $__XILINX_RAMB18_TDP18
endbram
bram $__XILINX_RAMB18_TDP9
- abits 12
+ abits 11
dbits 9
groups 2
ports 1 1
@@ -48,7 +48,7 @@ bram $__XILINX_RAMB18_TDP9
endbram
bram $__XILINX_RAMB18_TDP4
- abits 13
+ abits 12
dbits 4
groups 2
ports 1 1
@@ -60,7 +60,7 @@ bram $__XILINX_RAMB18_TDP4
endbram
bram $__XILINX_RAMB18_TDP2
- abits 14
+ abits 13
dbits 2
groups 2
ports 1 1
@@ -72,7 +72,7 @@ bram $__XILINX_RAMB18_TDP2
endbram
bram $__XILINX_RAMB18_TDP1
- abits 15
+ abits 14
dbits 1
groups 2
ports 1 1
@@ -94,14 +94,16 @@ match $__XILINX_RAMB18_SDP36
min bits 4096
min efficiency 5
shuffle_enable 4
- # or_next_if_better
+ or_next_if_better
endmatch
-# match $__XILINX_RAMB18_TDP18
-# shuffle_enable 2
-# or_next_if_better
-# endmatch
-#
+match $__XILINX_RAMB18_TDP18
+ min bits 4096
+ min efficiency 5
+ shuffle_enable 2
+ # or_next_if_better
+endmatch
+
# match $__XILINX_RAMB18_TDP9
# or_next_if_better
# endmatch
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index a0baeaf0..a2724fe3 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -167,10 +167,10 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
input CLK2;
input CLK3;
- input [8:0] A1ADDR;
+ input [9:0] A1ADDR;
output [17:0] A1DATA;
- input [8:0] B1ADDR;
+ input [9:0] B1ADDR;
input [17:0] B1DATA;
input [1:0] B1EN;
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
index dbefdb6e..ff0929da 100644
--- a/techlibs/xilinx/tests/bram1_tb.v
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -21,6 +21,21 @@ module bram1_tb #(
.RD_DATA(RD_DATA)
);
+ reg [63:0] xorshift64_state = 64'd88172645463325252;
+
+ task xorshift64_next;
+ begin
+ // see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
+ xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
+ xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
+ xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
+ end
+ endtask
+
+ reg [ABITS-1:0] randaddr1;
+ reg [ABITS-1:0] randaddr2;
+ reg [ABITS-1:0] randaddr3;
+
function [31:0] getaddr(input [3:0] n);
begin
case (n)
@@ -31,14 +46,19 @@ module bram1_tb #(
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
- 7: getaddr = 123456789;
- default: getaddr = 1 << (2*n-16);
+ 7: getaddr = randaddr1;
+ 8: getaddr = randaddr2;
+ 9: getaddr = randaddr3;
+ default: begin
+ getaddr = 1 << (2*n-16);
+ if (!getaddr) getaddr = xorshift64_state;
+ end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
- reg [DBITS-1:0] expected_rd;
+ reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
reg error_ind = 0;
@@ -47,12 +67,33 @@ module bram1_tb #(
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
+
+ xorshift64_next;
+ xorshift64_next;
+ xorshift64_next;
+ xorshift64_next;
+
+ randaddr1 = xorshift64_state;
+ xorshift64_next;
+
+ randaddr2 = xorshift64_state;
+ xorshift64_next;
+
+ randaddr3 = xorshift64_state;
+ xorshift64_next;
+
clk <= 0;
for (i = 0; i < 256; i = i+1) begin
- WR_DATA <= i;
+ if (DBITS > 64)
+ WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
+ else
+ WR_DATA <= xorshift64_state;
+ xorshift64_next;
WR_ADDR <= getaddr(i[7:4]);
+ xorshift64_next;
RD_ADDR <= getaddr(i[3:0]);
WR_EN <= ^i;
+ xorshift64_next;
#1; clk <= 1;
#1; clk <= 0;
@@ -65,13 +106,11 @@ module bram1_tb #(
if (WR_EN) memory[WR_ADDR] = WR_DATA;
end
- for (j = 0; j < DBITS; j = j+1) begin
- if (expected_rd[j] === 1'bx)
- expected_rd[j] = RD_DATA[j];
- end
+ for (j = 0; j < DBITS; j = j+1)
+ expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
- $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
- if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
+ $display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
+ if (expected_rd_masked !== RD_DATA) begin -> error; error_ind = ~error_ind; end
end
end
endmodule