Added read-enable to memory model

6 files changed, 36 insertions, 29 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2a56b3a1..a2dc466d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1494,7 +1494,7 @@ endmodule
 // --------------------------------------------------------
 `ifndef SIMLIB_NOMEM
 
-module \$memrd (CLK, ADDR, DATA);
+module \$memrd (CLK, EN, ADDR, DATA);
 
 parameter MEMID = "";
 parameter ABITS = 8;
@@ -1504,7 +1504,7 @@ parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
 parameter TRANSPARENT = 0;
 
-input CLK;
+input CLK, EN;
 input [ABITS-1:0] ADDR;
 output [WIDTH-1:0] DATA;
 
@@ -1568,7 +1568,7 @@ endmodule
 
 // --------------------------------------------------------
 
-module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
+module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
 parameter signed SIZE = 4;
@@ -1587,6 +1587,7 @@ parameter WR_CLK_ENABLE = 1'b1;
 parameter WR_CLK_POLARITY = 1'b1;
 
 input [RD_PORTS-1:0] RD_CLK;
+input [RD_PORTS-1:0] RD_EN;
 input [RD_PORTS*ABITS-1:0] RD_ADDR;
 output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
 
@@ -1626,7 +1627,7 @@ always @(RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA) begin
 	#`SIMLIB_MEMDELAY;
 `endif
 	for (i = 0; i < RD_PORTS; i = i+1) begin
-		if ((!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i]) && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
+		if (!RD_TRANSPARENT[i] && RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
 			// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
 			RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
 		end
diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt
index 05131b22..03d59611 100644
--- a/techlibs/ice40/brams.txt
+++ b/techlibs/ice40/brams.txt
@@ -5,7 +5,7 @@ bram $__ICE40_RAM4K_M0
   groups 2
   ports  1  1
   wrmode 0  1
-  enable 0 16
+  enable 1 16
   transp 0  0
   clocks 2  3
   clkpol 2  3
@@ -22,7 +22,7 @@ bram $__ICE40_RAM4K_M123
   groups 2
   ports  1 1
   wrmode 0 1
-  enable 0 1
+  enable 1 1
   transp 0 0
   clocks 2 3
   clkpol 2 3
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index f3674b4e..a82161c9 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -168,7 +168,7 @@ module \$__ICE40_RAM4K (
 endmodule
 
 
-module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter [0:0] CLKPOL2 = 1;
 	parameter [0:0] CLKPOL3 = 1;
 
@@ -179,6 +179,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [7:0] A1ADDR;
 	output [15:0] A1DATA;
+	input A1EN;
 
 	input [7:0] B1ADDR;
 	input [15:0] B1DATA;
@@ -213,7 +214,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 		.RADDR(A1ADDR_11),
 		.RCLK(CLK2),
 		.RCLKE(1'b1),
-		.RE(1'b1),
+		.RE(A1EN),
 		.WDATA(B1DATA),
 		.WADDR(B1ADDR_11),
 		.MASK(~B1EN),
@@ -223,7 +224,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	);
 endmodule
 
-module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 9;
 	parameter CFG_DBITS = 8;
 
@@ -242,6 +243,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [CFG_ABITS-1:0] A1ADDR;
 	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
 
 	input [CFG_ABITS-1:0] B1ADDR;
 	input [CFG_DBITS-1:0] B1DATA;
@@ -298,7 +300,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 		.RADDR(A1ADDR_11),
 		.RCLK(CLK2),
 		.RCLKE(1'b1),
-		.RE(1'b1),
+		.RE(A1EN),
 		.WDATA(B1DATA_16),
 		.WADDR(B1ADDR_11),
 		.WCLK(CLK3),
diff --git a/techlibs/xilinx/brams.txt b/techlibs/xilinx/brams.txt
index 894e714c..f1161114 100644
--- a/techlibs/xilinx/brams.txt
+++ b/techlibs/xilinx/brams.txt
@@ -6,7 +6,7 @@ bram $__XILINX_RAMB36_SDP
   groups 2
   ports  1 1
   wrmode 0 1
-  enable 0 8
+  enable 1 8
   transp 0 0
   clocks 2 3
   clkpol 2 3
@@ -19,7 +19,7 @@ bram $__XILINX_RAMB18_SDP
   groups 2
   ports  1 1
   wrmode 0 1
-  enable 0 4
+  enable 1 4
   transp 0 0
   clocks 2 3
   clkpol 2 3
@@ -42,9 +42,9 @@ bram $__XILINX_RAMB36_TDP
   groups 2
   ports  1 1
   wrmode 0 1
-  enable 0 4   @a10d36
-  enable 0 2   @a11d18
-  enable 0 1   @a12d9 @a13d4 @a14d2 @a15d1
+  enable 1 4   @a10d36
+  enable 1 2   @a11d18
+  enable 1 1   @a12d9 @a13d4 @a14d2 @a15d1
   transp 0 0
   clocks 2 3
   clkpol 2 3
@@ -65,8 +65,8 @@ bram $__XILINX_RAMB18_TDP
   groups 2
   ports  1 1
   wrmode 0 1
-  enable 0 2   @a10d18
-  enable 0 1   @a11d9 @a12d4 @a13d2 @a14d1
+  enable 1 2   @a10d18
+  enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
   transp 0 0
   clocks 2 3
   clkpol 2 3
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index cbfd4e1e..7ea49158 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -1,4 +1,4 @@
-module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CLKPOL2 = 1;
 	parameter CLKPOL3 = 1;
 	parameter [36863:0] INIT = 36864'bx;
@@ -8,6 +8,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [8:0] A1ADDR;
 	output [71:0] A1DATA;
+	input A1EN;
 
 	input [8:0] B1ADDR;
 	input [71:0] B1DATA;
@@ -47,7 +48,7 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 		.ADDRARDADDR(A1ADDR_16),
 		.CLKARDCLK(CLK2),
-		.ENARDEN(|1),
+		.ENARDEN(A1EN),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
 		.RSTREGARSTREG(|0),
@@ -65,7 +66,7 @@ endmodule
 
 // ------------------------------------------------------------------------
 
-module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CLKPOL2 = 1;
 	parameter CLKPOL3 = 1;
 	parameter [18431:0] INIT = 18432'bx;
@@ -75,6 +76,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [8:0] A1ADDR;
 	output [35:0] A1DATA;
+	input A1EN;
 
 	input [8:0] B1ADDR;
 	input [35:0] B1DATA;
@@ -111,7 +113,7 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 		.ADDRARDADDR(A1ADDR_14),
 		.CLKARDCLK(CLK2),
-		.ENARDEN(|1),
+		.ENARDEN(A1EN),
 		.REGCEAREGCE(|1),
 		.RSTRAMARSTRAM(|0),
 		.RSTREGARSTREG(|0),
@@ -129,7 +131,7 @@ endmodule
 
 // ------------------------------------------------------------------------
 
-module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 10;
 	parameter CFG_DBITS = 36;
 	parameter CFG_ENABLE_B = 4;
@@ -143,6 +145,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [CFG_ABITS-1:0] A1ADDR;
 	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
 
 	input [CFG_ABITS-1:0] B1ADDR;
 	input [CFG_DBITS-1:0] B1DATA;
@@ -181,7 +184,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 			.DOPADOP(DOP[3:0]),
 			.ADDRARDADDR(A1ADDR_16),
 			.CLKARDCLK(CLK2),
-			.ENARDEN(|1),
+			.ENARDEN(A1EN),
 			.REGCEAREGCE(|1),
 			.RSTRAMARSTRAM(|0),
 			.RSTREGARSTREG(|0),
@@ -219,7 +222,7 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 			.DOPADOP(DOP[3:0]),
 			.ADDRARDADDR(A1ADDR_16),
 			.CLKARDCLK(CLK2),
-			.ENARDEN(|1),
+			.ENARDEN(A1EN),
 			.REGCEAREGCE(|1),
 			.RSTRAMARSTRAM(|0),
 			.RSTREGARSTREG(|0),
@@ -242,7 +245,7 @@ endmodule
 
 // ------------------------------------------------------------------------
 
-module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	parameter CFG_ABITS = 10;
 	parameter CFG_DBITS = 18;
 	parameter CFG_ENABLE_B = 2;
@@ -256,6 +259,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
 	input [CFG_ABITS-1:0] A1ADDR;
 	output [CFG_DBITS-1:0] A1DATA;
+	input A1EN;
 
 	input [CFG_ABITS-1:0] B1ADDR;
 	input [CFG_DBITS-1:0] B1DATA;
@@ -294,7 +298,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 			.DOPADOP(DOP),
 			.ADDRARDADDR(A1ADDR_14),
 			.CLKARDCLK(CLK2),
-			.ENARDEN(|1),
+			.ENARDEN(A1EN),
 			.REGCEAREGCE(|1),
 			.RSTRAMARSTRAM(|0),
 			.RSTREGARSTREG(|0),
@@ -332,7 +336,7 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 			.DOPADOP(DOP),
 			.ADDRARDADDR(A1ADDR_14),
 			.CLKARDCLK(CLK2),
-			.ENARDEN(|1),
+			.ENARDEN(A1EN),
 			.REGCEAREGCE(|1),
 			.RSTRAMARSTRAM(|0),
 			.RSTREGARSTREG(|0),
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b3d4c214..ee67beba 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -79,7 +79,6 @@ struct SynthXilinxPass : public Pass {
 		log("\n");
 		log("    coarse:\n");
 		log("        synth -run coarse\n");
-		log("        dff2dffe\n");
 		log("\n");
 		log("    bram:\n");
 		log("        memory_bram -rules +/xilinx/brams.txt\n");
@@ -92,6 +91,7 @@ struct SynthXilinxPass : public Pass {
 		log("    fine:\n");
 		log("        opt -fast -full\n");
 		log("        memory_map\n");
+		log("        dff2dffe\n");
 		log("        opt -full\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
@@ -178,7 +178,6 @@ struct SynthXilinxPass : public Pass {
 		if (check_label(active, run_from, run_to, "coarse"))
 		{
 			Pass::call(design, "synth -run coarse");
-			Pass::call(design, "dff2dffe");
 		}
 
 		if (check_label(active, run_from, run_to, "bram"))
@@ -197,6 +196,7 @@ struct SynthXilinxPass : public Pass {
 		{
 			Pass::call(design, "opt -fast -full");
 			Pass::call(design, "memory_map");
+			Pass::call(design, "dff2dffe");
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 			Pass::call(design, "opt -fast");