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authorClifford Wolf <clifford@clifford.at>2013-03-14 11:15:00 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-14 11:15:00 +0100
commit11789db206276edf50f45f8d82e094a87643630c (patch)
tree273617ebcc76baca97a426345aeb0ae835073f6a /techlibs
parentde823ce964b93c0746b81867b29228cdbe00aae6 (diff)
More support code for $sr cells
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/simlib.v21
1 files changed, 21 insertions, 0 deletions
diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 17924254..29c13503 100644
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -642,6 +642,27 @@ endmodule
// --------------------------------------------------------
+module \$sr (S, R, Q);
+
+parameter WIDTH = 0;
+
+input CLK;
+input [WIDTH-1:0] S, R;
+output reg [WIDTH-1:0] Q;
+
+integer i;
+always @(S, R)
+ for (i = 0; i < WIDTH; i = i+1) begin
+ if (R[i])
+ Q[i] <= 0;
+ else if (S[i])
+ Q[i] <= 1;
+ end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$dff (CLK, D, Q);
parameter WIDTH = 0;