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authorClifford Wolf <clifford@clifford.at>2013-06-03 12:48:44 +0200
committerClifford Wolf <clifford@clifford.at>2013-06-03 12:48:44 +0200
commit29d6ebd961442d5df28a39dd907988480400fea6 (patch)
treec3164e9edb1fcef0c1fa1c247f91c8f3f87a314f /techlibs
parent21d9251e52c2a1807306fd4067de0750e45465c0 (diff)
Implemented technology mapping for multipliers (using array multiplier)
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/stdcells.v34
1 files changed, 30 insertions, 4 deletions
diff --git a/techlibs/stdcells.v b/techlibs/stdcells.v
index e4a034c6..01cfb9d1 100644
--- a/techlibs/stdcells.v
+++ b/techlibs/stdcells.v
@@ -946,7 +946,26 @@ wire [Y_WIDTH-1:0] A_buf, B_buf;
endmodule
-/****
+// --------------------------------------------------------
+
+module \$arraymul (A, B, Y);
+
+parameter WIDTH = 8;
+input [WIDTH-1:0] A, B;
+output [WIDTH-1:0] Y;
+
+wire [WIDTH*WIDTH-1:0] partials;
+
+genvar i;
+assign partials[WIDTH-1 : 0] = A[0] ? B : 0;
+generate for (i = 1; i < WIDTH; i = i+1) begin:gen
+ assign partials[WIDTH*(i+1)-1 : WIDTH*i] = (A[i] ? B << i : 0) + partials[WIDTH*i-1 : WIDTH*(i-1)];
+end endgenerate
+
+assign Y = partials[WIDTH*WIDTH-1 : WIDTH*(WIDTH-1)];
+
+endmodule
+
// --------------------------------------------------------
module \$mul (A, B, Y);
@@ -961,13 +980,20 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-wire signed [A_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
-wire signed [B_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
+wire signed [Y_WIDTH:0] buffer_a = A_SIGNED ? $signed(A) : A;
+wire signed [Y_WIDTH:0] buffer_b = B_SIGNED ? $signed(B) : B;
-assign Y = buffer_a * buffer_b;
+\$arraymul #(
+ .WIDTH(Y_WIDTH)
+) arraymul (
+ .A(buffer_a),
+ .B(buffer_b),
+ .Y(Y)
+);
endmodule
+/****
// --------------------------------------------------------
module \$div (A, B, Y);