diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-10-26 22:28:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-10-26 22:28:42 +0200 |
| commit | 4007b41d40147bf3d282f25f6c177a17fb2a8f76 (patch) | |
| tree | 1b18feb3bd01fa0681c86cb49d8b3efd6d3192e3 /techlibs | |
| parent | ceb971eab9802e695e52064d4f7369ab6daea3b3 (diff) | |
Improved xilinx mojo_counter example
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx7/example_mojo_counter/example.sh | 5 | ||||
| -rw-r--r-- | techlibs/xilinx7/example_mojo_counter/example.v | 2 |
2 files changed, 5 insertions, 2 deletions
diff --git a/techlibs/xilinx7/example_mojo_counter/example.sh b/techlibs/xilinx7/example_mojo_counter/example.sh index 17fc650e..87af0ea3 100644 --- a/techlibs/xilinx7/example_mojo_counter/example.sh +++ b/techlibs/xilinx7/example_mojo_counter/example.sh @@ -19,11 +19,14 @@ abc -lut 6; opt # map internal cells to FPGA cells techmap -map ../cells.v; opt +# insert i/o buffers +iopadmap -outpad OBUF I:O -inpad BUFGP O:I + # write netlist write_edif synth.edif EOT -cat > synth.ut <<- EOT +cat > bitgen.ut <<- EOT -w -g DebugBitstream:No -g Binary:no diff --git a/techlibs/xilinx7/example_mojo_counter/example.v b/techlibs/xilinx7/example_mojo_counter/example.v index 1327d9b8..8e79942e 100644 --- a/techlibs/xilinx7/example_mojo_counter/example.v +++ b/techlibs/xilinx7/example_mojo_counter/example.v @@ -7,7 +7,7 @@ output led_3, led_2, led_1, led_0; reg [31:0] counter; always @(posedge clk) - counter <= counter + 1; + counter <= 32'b_1010_1010_1010_1010_1010_1010_1010_1010; // counter + 1; assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24; |