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authorClifford Wolf <clifford@clifford.at>2014-09-08 17:09:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-08 17:09:39 +0200
commit44b5bd4b631874e5ed083d5de75f5b87431f935f (patch)
treeaf7523f30794210c78d89f9a3f859c9c2ffdacb0 /techlibs
parentfcb46138cebd57587d35489cef3a3a48ebe40bcf (diff)
Fixed simlib $macc model for xilinx xsim
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/common/simlib.v16
1 files changed, 15 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index dd12bd39..0ad8d14b 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -806,9 +806,23 @@ input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output reg [Y_WIDTH-1:0] Y;
+// Xilinx XSIM does not like $clog2() below..
+function integer my_clog2;
+ input integer v;
+ begin
+ if (v > 0)
+ v = v - 1;
+ my_clog2 = 0;
+ while (v) begin
+ v = v >> 1;
+ my_clog2 = my_clog2 + 1;
+ end
+ end
+endfunction
+
localparam integer num_bits = CONFIG[3:0];
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
-localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
+localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;