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authorClifford Wolf <clifford@clifford.at>2014-08-16 18:18:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 18:29:39 +0200
commit47c2637a961839f1eb1a0386f7e54d94be50bc10 (patch)
tree2db3bfbabf1ad7ca21176c2639b565720655fb8b /techlibs
parent56a30cf42c6a40f265a67df6e2c5fa74657fbf5b (diff)
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/common/simcells.v42
1 files changed, 42 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 7c8a47dd..a2a37735 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -37,24 +37,66 @@ output Y;
assign Y = A & B;
endmodule
+module \$_NAND_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A & B);
+endmodule
+
module \$_OR_ (A, B, Y);
input A, B;
output Y;
assign Y = A | B;
endmodule
+module \$_NOR_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A | B);
+endmodule
+
module \$_XOR_ (A, B, Y);
input A, B;
output Y;
assign Y = A ^ B;
endmodule
+module \$_XNOR_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A ^ B);
+endmodule
+
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
assign Y = S ? B : A;
endmodule
+module \$_AOI3_ (A, B, C, Y);
+input A, B, C;
+output Y;
+assign Y = ~((A & B) | C);
+endmodule
+
+module \$_OAI3_ (A, B, C, Y);
+input A, B, C;
+output Y;
+assign Y = ~((A | B) & C);
+endmodule
+
+module \$_AOI4_ (A, B, C, D, Y);
+input A, B, C, D;
+output Y;
+assign Y = ~((A & B) | (C & D));
+endmodule
+
+module \$_OAI4_ (A, B, C, D, Y);
+input A, B, C, D;
+output Y;
+assign Y = ~((A | B) & (C | D));
+endmodule
+
module \$_SR_NN_ (S, R, Q);
input S, R;
output reg Q;