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authorClifford Wolf <clifford@clifford.at>2013-09-03 19:10:25 +0200
committerClifford Wolf <clifford@clifford.at>2013-09-03 19:10:25 +0200
commit70476e24314454d1cc95a4cba24a3c5efce64d64 (patch)
tree1f6f6f53ff47e2627a3ae272d05091dd3561a63f /techlibs
parent73914d1a414ad2277beca87fe1c52a564a796481 (diff)
parent09e200797a5f1aca9cadf9300f09b3b56191c39d (diff)
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx7/run_testbench.sh12
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/xilinx7/run_testbench.sh b/techlibs/xilinx7/run_testbench.sh
index 970fef46..31da59eb 100644
--- a/techlibs/xilinx7/run_testbench.sh
+++ b/techlibs/xilinx7/run_testbench.sh
@@ -2,7 +2,7 @@
set -ex
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
+XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
../../yosys - <<- EOT
# read design
@@ -20,6 +20,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
# write netlist
write_verilog -noattr testbench_synth.v
+ write_edif testbench_synth.edif
EOT
iverilog -o testbench_gold counter_tb.v counter.v
@@ -35,7 +36,14 @@ else
exit 1
fi
+if [ "$*" = "-map" ]; then
+ set -x
+ $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
+ $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
+fi
+
if [ "$*" = "-clean" ]; then
- rm -f testbench_{synth.v,{gold,gate}{,.txt}}
+ rm -rf netlist.lst _xmsgs/
+ rm -f testbench_{synth,gold,gate}*
fi