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authorClifford Wolf <clifford@clifford.at>2013-10-27 09:52:00 +0100
committerClifford Wolf <clifford@clifford.at>2013-10-27 09:58:53 +0100
commit88cd2eadf5f889eb0187f25789a9e6bd95ccdb7b (patch)
treedb06570b693a049a3e0ce696898df936230b3cc1 /techlibs
parent4a3669d871dccf7ff772ad584b9f1271f75e4eb5 (diff)
Cleanups in xilinx examples
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.sh63
-rw-r--r--techlibs/xilinx/example_sim_counter/run_sim.sh23
-rw-r--r--techlibs/xilinx/example_sim_counter/run_testbench.sh86
3 files changed, 28 insertions, 144 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh
index 466fadad..74a0c117 100644
--- a/techlibs/xilinx/example_mojo_counter/example.sh
+++ b/techlibs/xilinx/example_mojo_counter/example.sh
@@ -2,70 +2,17 @@
set -ex
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/
+XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
XILINX_PART=xc6slx9-2-tqg144
-../../../yosys - << EOT
-# read design
-read_verilog example.v
-
-# high-level synthesis
-hierarchy -check -top top
-proc; opt; fsm; opt; techmap; opt
-
-# mapping logic to LUTs using Berkeley ABC
-abc -lut 6; opt
-
-# map internal cells to FPGA cells
-techmap -map ../cells.v; opt
-
-# insert clock buffers
-select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d
-iopadmap -inpad BUFGP O:I @clocks
-
-# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n
-
-# write netlist
-write_edif synth.edif
-EOT
-
-cat > bitgen.ut <<- EOT
- -w
- -g DebugBitstream:No
- -g Binary:no
- -g CRC:Enable
- -g Reset_on_err:No
- -g ConfigRate:2
- -g ProgPin:PullUp
- -g TckPin:PullUp
- -g TdiPin:PullUp
- -g TdoPin:PullUp
- -g TmsPin:PullUp
- -g UnusedPin:PullDown
- -g UserID:0xFFFFFFFF
- -g ExtMasterCclk_en:No
- -g SPI_buswidth:1
- -g TIMER_CFG:0xFFFF
- -g multipin_wakeup:No
- -g StartUpClk:CClk
- -g DONE_cycle:4
- -g GTS_cycle:5
- -g GWE_cycle:6
- -g LCK_cycle:NoWait
- -g Security:None
- -g DonePipe:No
- -g DriveDone:No
- -g en_sw_gsr:No
- -g drive_awake:No
- -g sw_clk:Startupclk
- -g sw_gwe_cycle:5
- -g sw_gts_cycle:4
+../../../yosys - <<- EOT
+ read_verilog example.v
+ synth_xilinx -edif synth.edif
EOT
$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
-$XILINX_DIR/bin/lin64/bitgen -f bitgen.ut placed.ncd example.bit constraints.pcf
+$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf
diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
new file mode 100644
index 00000000..e26d00db
--- /dev/null
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+set -ex
+
+XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
+
+../../../yosys -p 'synth_xilinx -top counter; write_verilog -noattr testbench_synth.v' counter.v
+
+iverilog -o testbench_gold counter_tb.v counter.v
+iverilog -o testbench_gate counter_tb.v testbench_synth.v \
+ $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+
+./testbench_gold > testbench_gold.txt
+./testbench_gate > testbench_gate.txt
+
+if diff -u testbench_gold.txt testbench_gate.txt; then
+ set +x; echo; echo; banner " PASS "
+else
+ exit 1
+fi
+
+rm -f testbench_{synth,gold,gate,mapped}*
+
diff --git a/techlibs/xilinx/example_sim_counter/run_testbench.sh b/techlibs/xilinx/example_sim_counter/run_testbench.sh
deleted file mode 100644
index b4251f49..00000000
--- a/techlibs/xilinx/example_sim_counter/run_testbench.sh
+++ /dev/null
@@ -1,86 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/
-
-../../yosys - <<- EOT
- # read design
- read_verilog counter.v
-
- # high-level synthesis
- hierarchy -check -top counter
- proc; opt; fsm; opt; techmap; opt
-
- # mapping logic to LUTs using Berkeley ABC
- abc -lut 6; opt
-
- # map internal cells to FPGA cells
- techmap -map cells.v; opt
-
- # write netlist
- write_verilog -noattr testbench_synth.v
- write_edif testbench_synth.edif
-EOT
-
-iverilog -o testbench_gold counter_tb.v counter.v
-iverilog -o testbench_gate counter_tb.v testbench_synth.v \
- $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
-
-./testbench_gold > testbench_gold.txt
-./testbench_gate > testbench_gate.txt
-
-if diff -u testbench_gold.txt testbench_gate.txt; then
- set +x; echo; echo; banner " PASS "
-else
- exit 1
-fi
-
-if [ "$*" = "-map" ]; then
- set -x
-
- cat > testbench_synth.ut <<- EOT
- -w
- -g DebugBitstream:No
- -g Binary:no
- -g CRC:Enable
- -g Reset_on_err:No
- -g ConfigRate:2
- -g ProgPin:PullUp
- -g TckPin:PullUp
- -g TdiPin:PullUp
- -g TdoPin:PullUp
- -g TmsPin:PullUp
- -g UnusedPin:PullDown
- -g UserID:0xFFFFFFFF
- -g ExtMasterCclk_en:No
- -g SPI_buswidth:1
- -g TIMER_CFG:0xFFFF
- -g multipin_wakeup:No
- -g StartUpClk:CClk
- -g DONE_cycle:4
- -g GTS_cycle:5
- -g GWE_cycle:6
- -g LCK_cycle:NoWait
- -g Security:None
- -g DonePipe:No
- -g DriveDone:No
- -g en_sw_gsr:No
- -g drive_awake:No
- -g sw_clk:Startupclk
- -g sw_gwe_cycle:5
- -g sw_gts_cycle:4
- EOT
-
- $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif
- $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth
- $XILINX_DIR/bin/lin64/map -p xc7k70t-fbg676-1 -w -o testbench_mapped.ncd testbench_synth prffile.pcf
- $XILINX_DIR/bin/lin64/par -w testbench_mapped.ncd testbench_synth.ncd prffile.pcf
- $XILINX_DIR/bin/lin64/bitgen -f testbench_synth.ut testbench_synth.ncd
-fi
-
-if [ "$*" = "-clean" ]; then
- rm -rf netlist.lst _xmsgs/ prffile.pcf
- rm -f testbench_{synth,gold,gate,mapped}*
-fi
-