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authorClifford Wolf <clifford@clifford.at>2013-11-06 22:59:45 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-06 22:59:45 +0100
commitb41740060b28039c7e01fede41e6affb91867e02 (patch)
tree70423eda7b4254b17ec5f9770afc29a92b1d37fe /techlibs
parentf485962c5e0866d84e56c7c95ded2cb9c5cba190 (diff)
Fixed techmap of $gt and $ge with multi-bit outputs
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/common/stdcells.v16
1 files changed, 14 insertions, 2 deletions
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index d89b39b8..ca73f5bc 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -855,9 +855,15 @@ output [Y_WIDTH-1:0] Y;
) ge_via_le (
.A(B),
.B(A),
- .Y(Y)
+ .Y(Y[0])
);
+generate
+ if (Y_WIDTH > 1) begin:V
+ assign Y[Y_WIDTH-1:1] = 0;
+ end
+endgenerate
+
endmodule
// --------------------------------------------------------
@@ -882,9 +888,15 @@ output [Y_WIDTH-1:0] Y;
) gt_via_lt (
.A(B),
.B(A),
- .Y(Y)
+ .Y(Y[0])
);
+generate
+ if (Y_WIDTH > 1) begin:V
+ assign Y[Y_WIDTH-1:1] = 0;
+ end
+endgenerate
+
endmodule
// --------------------------------------------------------