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authorClifford Wolf <clifford@clifford.at>2013-09-14 11:23:45 +0200
committerClifford Wolf <clifford@clifford.at>2013-09-14 11:23:45 +0200
commitbbe5aa446b413c6298a4b0b13f6fabcd6c984cb6 (patch)
tree1553bf01f0c804ae86f887a0304e70395f15052c /techlibs
parent70476e24314454d1cc95a4cba24a3c5efce64d64 (diff)
Added spice backend
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/cmos/cmos_cells.lib32
-rw-r--r--techlibs/cmos/cmos_cells.v23
-rw-r--r--techlibs/cmos/counter.v12
-rw-r--r--techlibs/cmos/counter.ys11
4 files changed, 78 insertions, 0 deletions
diff --git a/techlibs/cmos/cmos_cells.lib b/techlibs/cmos/cmos_cells.lib
new file mode 100644
index 00000000..1d7b8279
--- /dev/null
+++ b/techlibs/cmos/cmos_cells.lib
@@ -0,0 +1,32 @@
+library(demo) {
+ cell(NOT) {
+ area: 3;
+ pin(A) { direction: input; }
+ pin(Y) { direction: output;
+ function: "A'"; }
+ }
+ cell(NAND) {
+ area: 4;
+ pin(A) { direction: input; }
+ pin(B) { direction: input; }
+ pin(Y) { direction: output;
+ function: "(A*B)'"; }
+ }
+ cell(NOR) {
+ area: 4;
+ pin(A) { direction: input; }
+ pin(B) { direction: input; }
+ pin(Y) { direction: output;
+ function: "(A+B)'"; }
+ }
+ cell(DFF) {
+ area: 18;
+ ff(IQ, IQN) { clocked_on: C;
+ next_state: D; }
+ pin(C) { direction: input;
+ clock: true; }
+ pin(D) { direction: input; }
+ pin(Q) { direction: output;
+ function: "IQ"; }
+ }
+}
diff --git a/techlibs/cmos/cmos_cells.v b/techlibs/cmos/cmos_cells.v
new file mode 100644
index 00000000..802f5871
--- /dev/null
+++ b/techlibs/cmos/cmos_cells.v
@@ -0,0 +1,23 @@
+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+ Q <= D;
+endmodule
+
diff --git a/techlibs/cmos/counter.v b/techlibs/cmos/counter.v
new file mode 100644
index 00000000..72208bd8
--- /dev/null
+++ b/techlibs/cmos/counter.v
@@ -0,0 +1,12 @@
+module counter (clk, rst, en, count);
+
+ input clk, rst, en;
+ output reg [3:0] count;
+
+ always @(posedge clk)
+ if (rst)
+ count <= 4'd0;
+ else if (en)
+ count <= count + 4'd1;
+
+endmodule
diff --git a/techlibs/cmos/counter.ys b/techlibs/cmos/counter.ys
new file mode 100644
index 00000000..81430f68
--- /dev/null
+++ b/techlibs/cmos/counter.ys
@@ -0,0 +1,11 @@
+
+read_verilog counter.v
+read_verilog -lib cmos_cells.v
+
+proc;; memory;; techmap;;
+dfflibmap -liberty cmos_cells.lib
+abc -liberty cmos_cells.lib;;
+
+write_verilog synth.v
+write_spice synth.sp
+