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authorClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
commitd46bac330520f91ee5bf8027abe98a8f9389f696 (patch)
treed1b87a2409d082fa281d2c9ea100e94c69a43912 /techlibs
parent1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 (diff)
Added "$fa" cell type
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/common/simlib.v16
-rw-r--r--techlibs/common/techmap.v12
2 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 465efc0a..c170945e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -443,6 +443,22 @@ endmodule
// --------------------------------------------------------
+module \$fa (A, B, C, X, Y);
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0] A, B, C;
+output [WIDTH-1:0] X, Y;
+
+wire [WIDTH-1:0] t1, t2, t3;
+
+assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
+assign Y = t1 ^ C, X = t2 | t3;
+
+endmodule
+
+// --------------------------------------------------------
+
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index dc52ca5f..05074637 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -246,6 +246,18 @@ endmodule
// ALU Infrastructure
// --------------------------------------------------------
+module \$fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ input [WIDTH-1:0] A, B, C;
+ output [WIDTH-1:0] X, Y;
+
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
+ assign Y = t1 ^ C, X = t2 | t3;
+endmodule
+
module \$__alu_ripple (A, B, CI, X, Y, CO);
parameter WIDTH = 1;