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authorClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 14:11:40 +0200
commitf092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch)
tree2f09add560746030249fe333e551de2f113bccdb /techlibs
parentbf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff)
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/common/simcells.v4
-rw-r--r--techlibs/common/techmap.v2
2 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index d492c2f1..7c8a47dd 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -20,12 +20,12 @@
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
- * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
+ * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/
-module \$_INV_ (A, Y);
+module \$_NOT_ (A, Y);
input A;
output Y;
assign Y = ~A;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 7a4f6b27..190002c0 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -20,7 +20,7 @@
* The internal logic cell technology mapper.
*
* This verilog library contains the mapping of internal cells (e.g. $not with
- * variable bit width) to the internal logic cells (such as the single bit $_INV_
+ * variable bit width) to the internal logic cells (such as the single bit $_NOT_
* gate). Usually this logic network is then mapped to the actual technology
* using e.g. the "abc" pass.
*