summaryrefslogtreecommitdiff
path: root/techlibs
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2015-04-18 09:33:34 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-18 09:33:34 +0200
commitf564a658517f510dce12c5ef8bcc2a9ec9dd055b (patch)
tree03574547329d666ad0e229fa2529fd254a083273 /techlibs
parentf78fa718be5ff611547dbadce5f2dc3e9fb59384 (diff)
Added ice40 test_arith
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/ice40/tests/test_arith.v3
-rw-r--r--techlibs/ice40/tests/test_arith.ys10
2 files changed, 13 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_arith.v b/techlibs/ice40/tests/test_arith.v
new file mode 100644
index 00000000..77f79b97
--- /dev/null
+++ b/techlibs/ice40/tests/test_arith.v
@@ -0,0 +1,3 @@
+module test(input [4:0] a, b, c, output [4:0] y);
+ assign y = ((a+b) ^ (a-c)) - ((a*b) + (a*c) - (b*c));
+endmodule
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
new file mode 100644
index 00000000..160c767f
--- /dev/null
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -0,0 +1,10 @@
+read_verilog test_arith.v
+synth_ice40
+techmap -map ../cells_sim.v
+rename test gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter