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author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:51 +0000 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:51 +0000 |
commit | 1f6bb85359149a016811e7e7fef980c3d45211e7 (patch) | |
tree | 749672f9a104cbfb25bb02acad6cb731724b9d56 /tests/arch/run-test.sh | |
parent | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff) |
New upstream version 0.9
Diffstat (limited to 'tests/arch/run-test.sh')
-rwxr-xr-x | tests/arch/run-test.sh | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh new file mode 100755 index 00000000..5292d161 --- /dev/null +++ b/tests/arch/run-test.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -e + +echo "Running syntax check on arch sim models" +for arch in ../../techlibs/*; do + find $arch -name cells_sim.v | while read path; do + echo -n "Test $path ->" + iverilog -t null -I$arch $path + echo " ok" + done +done + +for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do + echo -n "Test $path ->" + iverilog -t null $path + echo " ok" +done |