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authorClifford Wolf <clifford@clifford.at>2013-01-05 11:13:26 +0100
committerClifford Wolf <clifford@clifford.at>2013-01-05 11:13:26 +0100
commit7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch)
tree18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld
initial import
Diffstat (limited to 'tests/asicworld')
-rw-r--r--tests/asicworld/README1
-rw-r--r--tests/asicworld/code_hdl_models_GrayCounter.v33
-rw-r--r--tests/asicworld/code_hdl_models_arbiter.v123
-rw-r--r--tests/asicworld/code_hdl_models_arbiter_tb.v62
-rw-r--r--tests/asicworld/code_hdl_models_cam.v60
-rw-r--r--tests/asicworld/code_hdl_models_clk_div.v27
-rw-r--r--tests/asicworld/code_hdl_models_clk_div_45.v54
-rw-r--r--tests/asicworld/code_hdl_models_d_ff_gates.v29
-rw-r--r--tests/asicworld/code_hdl_models_d_latch_gates.v15
-rw-r--r--tests/asicworld/code_hdl_models_decoder_2to4_gates.v14
-rw-r--r--tests/asicworld/code_hdl_models_decoder_using_assign.v20
-rw-r--r--tests/asicworld/code_hdl_models_decoder_using_case.v43
-rw-r--r--tests/asicworld/code_hdl_models_dff_async_reset.v30
-rw-r--r--tests/asicworld/code_hdl_models_dff_sync_reset.v30
-rw-r--r--tests/asicworld/code_hdl_models_dlatch_reset.v30
-rw-r--r--tests/asicworld/code_hdl_models_encoder_4to2_gates.v8
-rw-r--r--tests/asicworld/code_hdl_models_encoder_using_case.v42
-rw-r--r--tests/asicworld/code_hdl_models_encoder_using_if.v58
-rw-r--r--tests/asicworld/code_hdl_models_full_adder_gates.v18
-rw-r--r--tests/asicworld/code_hdl_models_full_subtracter_gates.v20
-rw-r--r--tests/asicworld/code_hdl_models_gray_counter.v33
-rw-r--r--tests/asicworld/code_hdl_models_half_adder_gates.v14
-rw-r--r--tests/asicworld/code_hdl_models_lfsr.v35
-rw-r--r--tests/asicworld/code_hdl_models_lfsr_updown.v35
-rw-r--r--tests/asicworld/code_hdl_models_misc1.v22
-rw-r--r--tests/asicworld/code_hdl_models_mux21_switch.v22
-rw-r--r--tests/asicworld/code_hdl_models_mux_2to1_gates.v18
-rw-r--r--tests/asicworld/code_hdl_models_mux_using_assign.v22
-rw-r--r--tests/asicworld/code_hdl_models_mux_using_case.v28
-rw-r--r--tests/asicworld/code_hdl_models_mux_using_if.v29
-rw-r--r--tests/asicworld/code_hdl_models_nand_switch.v14
-rw-r--r--tests/asicworld/code_hdl_models_one_hot_cnt.v31
-rw-r--r--tests/asicworld/code_hdl_models_parallel_crc.v53
-rw-r--r--tests/asicworld/code_hdl_models_parity_using_assign.v21
-rw-r--r--tests/asicworld/code_hdl_models_parity_using_bitwise.v16
-rw-r--r--tests/asicworld/code_hdl_models_parity_using_function.v29
-rw-r--r--tests/asicworld/code_hdl_models_pri_encoder_using_assign.v36
-rw-r--r--tests/asicworld/code_hdl_models_ram_sp_ar_sw.v58
-rw-r--r--tests/asicworld/code_hdl_models_ram_sp_sr_sw.v62
-rw-r--r--tests/asicworld/code_hdl_models_rom_using_case.v42
-rw-r--r--tests/asicworld/code_hdl_models_serial_crc.v54
-rw-r--r--tests/asicworld/code_hdl_models_t_gate_switch.v11
-rw-r--r--tests/asicworld/code_hdl_models_tff_async_reset.v27
-rw-r--r--tests/asicworld/code_hdl_models_tff_sync_reset.v27
-rw-r--r--tests/asicworld/code_hdl_models_uart.v154
-rw-r--r--tests/asicworld/code_hdl_models_up_counter.v29
-rw-r--r--tests/asicworld/code_hdl_models_up_counter_load.v32
-rw-r--r--tests/asicworld/code_hdl_models_up_down_counter.v29
-rw-r--r--tests/asicworld/code_specman_switch_fabric.v82
-rw-r--r--tests/asicworld/code_tidbits_asyn_reset.v18
-rw-r--r--tests/asicworld/code_tidbits_blocking.v17
-rw-r--r--tests/asicworld/code_tidbits_fsm_using_always.v91
-rw-r--r--tests/asicworld/code_tidbits_fsm_using_function.v94
-rw-r--r--tests/asicworld/code_tidbits_fsm_using_single_always.v63
-rw-r--r--tests/asicworld/code_tidbits_nonblocking.v17
-rw-r--r--tests/asicworld/code_tidbits_reg_combo_example.v13
-rw-r--r--tests/asicworld/code_tidbits_reg_seq_example.v15
-rw-r--r--tests/asicworld/code_tidbits_syn_reset.v19
-rw-r--r--tests/asicworld/code_tidbits_wire_example.v9
-rw-r--r--tests/asicworld/code_verilog_tutorial_addbit.v24
-rw-r--r--tests/asicworld/code_verilog_tutorial_always_example.v11
-rw-r--r--tests/asicworld/code_verilog_tutorial_bus_con.v8
-rw-r--r--tests/asicworld/code_verilog_tutorial_comment.v25
-rw-r--r--tests/asicworld/code_verilog_tutorial_counter.v19
-rw-r--r--tests/asicworld/code_verilog_tutorial_counter_tb.v113
-rw-r--r--tests/asicworld/code_verilog_tutorial_d_ff.v14
-rw-r--r--tests/asicworld/code_verilog_tutorial_decoder.v14
-rw-r--r--tests/asicworld/code_verilog_tutorial_decoder_always.v20
-rw-r--r--tests/asicworld/code_verilog_tutorial_escape_id.v14
-rw-r--r--tests/asicworld/code_verilog_tutorial_explicit.v35
-rw-r--r--tests/asicworld/code_verilog_tutorial_first_counter.v47
-rw-r--r--tests/asicworld/code_verilog_tutorial_first_counter_tb.v36
-rw-r--r--tests/asicworld/code_verilog_tutorial_flip_flop.v15
-rw-r--r--tests/asicworld/code_verilog_tutorial_fsm_full.v114
-rw-r--r--tests/asicworld/code_verilog_tutorial_fsm_full_tb.v48
-rw-r--r--tests/asicworld/code_verilog_tutorial_good_code.v18
-rw-r--r--tests/asicworld/code_verilog_tutorial_if_else.v13
-rw-r--r--tests/asicworld/code_verilog_tutorial_multiply.v8
-rw-r--r--tests/asicworld/code_verilog_tutorial_mux_21.v9
-rw-r--r--tests/asicworld/code_verilog_tutorial_n_out_primitive.v13
-rw-r--r--tests/asicworld/code_verilog_tutorial_parallel_if.v21
-rw-r--r--tests/asicworld/code_verilog_tutorial_parity.v41
-rw-r--r--tests/asicworld/code_verilog_tutorial_simple_function.v10
-rw-r--r--tests/asicworld/code_verilog_tutorial_simple_if.v11
-rw-r--r--tests/asicworld/code_verilog_tutorial_task_global.v12
-rw-r--r--tests/asicworld/code_verilog_tutorial_tri_buf.v9
-rw-r--r--tests/asicworld/code_verilog_tutorial_v2k_reg.v24
-rw-r--r--tests/asicworld/code_verilog_tutorial_which_clock.v12
-rwxr-xr-xtests/asicworld/run-test.sh3
89 files changed, 2899 insertions, 0 deletions
diff --git a/tests/asicworld/README b/tests/asicworld/README
new file mode 100644
index 00000000..0e96edb7
--- /dev/null
+++ b/tests/asicworld/README
@@ -0,0 +1 @@
+Borrowed verilog examples from http://www.asic-world.com/.
diff --git a/tests/asicworld/code_hdl_models_GrayCounter.v b/tests/asicworld/code_hdl_models_GrayCounter.v
new file mode 100644
index 00000000..23f0da04
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_GrayCounter.v
@@ -0,0 +1,33 @@
+//==========================================
+// Function : Code Gray counter.
+// Coder : Alex Claros F.
+// Date : 15/May/2005.
+//=======================================
+
+module GrayCounter
+ #(parameter COUNTER_WIDTH = 4)
+
+ (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
+
+ input wire Enable_in, //Count enable.
+ input wire Clear_in, //Count reset.
+
+ input wire Clk);
+
+ /////////Internal connections & variables///////
+ reg [COUNTER_WIDTH-1:0] BinaryCount;
+
+ /////////Code///////////////////////
+
+ always @ (posedge Clk)
+ if (Clear_in) begin
+ BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with
+ GrayCount_out <= {COUNTER_WIDTH{1'b 0}}; // first 'Enable_in'.
+ end
+ else if (Enable_in) begin
+ BinaryCount <= BinaryCount + 1;
+ GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
+ BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
+ end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_arbiter.v b/tests/asicworld/code_hdl_models_arbiter.v
new file mode 100644
index 00000000..978e1987
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_arbiter.v
@@ -0,0 +1,123 @@
+//----------------------------------------------------
+// A four level, round-robin arbiter. This was
+// orginally coded by WD Peterson in VHDL.
+//----------------------------------------------------
+module arbiter (
+ clk,
+ rst,
+ req3,
+ req2,
+ req1,
+ req0,
+ gnt3,
+ gnt2,
+ gnt1,
+ gnt0
+);
+// --------------Port Declaration-----------------------
+input clk;
+input rst;
+input req3;
+input req2;
+input req1;
+input req0;
+output gnt3;
+output gnt2;
+output gnt1;
+output gnt0;
+
+//--------------Internal Registers----------------------
+wire [1:0] gnt ;
+wire comreq ;
+wire beg ;
+wire [1:0] lgnt ;
+wire lcomreq ;
+reg lgnt0 ;
+reg lgnt1 ;
+reg lgnt2 ;
+reg lgnt3 ;
+reg lasmask ;
+reg lmask0 ;
+reg lmask1 ;
+reg ledge ;
+
+//--------------Code Starts Here-----------------------
+always @ (posedge clk)
+if (rst) begin
+ lgnt0 <= 0;
+ lgnt1 <= 0;
+ lgnt2 <= 0;
+ lgnt3 <= 0;
+end else begin
+ lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
+ | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
+ | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
+ | (~lcomreq & lmask1 & lmask0 & req0 )
+ | ( lcomreq & lgnt0 );
+ lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
+ | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
+ | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
+ | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
+ | ( lcomreq & lgnt1);
+ lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
+ | (~lcomreq & ~lmask1 & lmask0 & req2)
+ | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
+ | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
+ | ( lcomreq & lgnt2);
+ lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
+ | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
+ | (~lcomreq & lmask1 & ~lmask0 & req3)
+ | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
+ | ( lcomreq & lgnt3);
+end
+
+//----------------------------------------------------
+// lasmask state machine.
+//----------------------------------------------------
+assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
+always @ (posedge clk)
+begin
+ lasmask <= (beg & ~ledge & ~lasmask);
+ ledge <= (beg & ~ledge & lasmask)
+ | (beg & ledge & ~lasmask);
+end
+
+//----------------------------------------------------
+// comreq logic.
+//----------------------------------------------------
+assign lcomreq = ( req3 & lgnt3 )
+ | ( req2 & lgnt2 )
+ | ( req1 & lgnt1 )
+ | ( req0 & lgnt0 );
+
+//----------------------------------------------------
+// Encoder logic.
+//----------------------------------------------------
+assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
+
+//----------------------------------------------------
+// lmask register.
+//----------------------------------------------------
+always @ (posedge clk )
+if( rst ) begin
+ lmask1 <= 0;
+ lmask0 <= 0;
+end else if(lasmask) begin
+ lmask1 <= lgnt[1];
+ lmask0 <= lgnt[0];
+end else begin
+ lmask1 <= lmask1;
+ lmask0 <= lmask0;
+end
+
+assign comreq = lcomreq;
+assign gnt = lgnt;
+//----------------------------------------------------
+// Drive the outputs
+//----------------------------------------------------
+assign gnt3 = lgnt3;
+assign gnt2 = lgnt2;
+assign gnt1 = lgnt1;
+assign gnt0 = lgnt0;
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v
new file mode 100644
index 00000000..5e7bf46b
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_arbiter_tb.v
@@ -0,0 +1,62 @@
+module testbench ();
+
+reg clk;
+reg rst;
+reg req3;
+reg req2;
+reg req1;
+reg req0;
+wire gnt3;
+wire gnt2;
+wire gnt1;
+wire gnt0;
+
+// Clock generator
+always #1 clk = ~clk;
+
+initial begin
+ $dumpfile ("arbiter.vcd");
+ $dumpvars();
+ clk = 0;
+ rst = 1;
+ req0 = 0;
+ req1 = 0;
+ req2 = 0;
+ req3 = 0;
+ #10 rst = 0;
+ repeat (1) @ (posedge clk);
+ req0 <= 1;
+ repeat (1) @ (posedge clk);
+ req0 <= 0;
+ repeat (1) @ (posedge clk);
+ req0 <= 1;
+ req1 <= 1;
+ repeat (1) @ (posedge clk);
+ req2 <= 1;
+ req1 <= 0;
+ repeat (1) @ (posedge clk);
+ req3 <= 1;
+ req2 <= 0;
+ repeat (1) @ (posedge clk);
+ req3 <= 0;
+ repeat (1) @ (posedge clk);
+ req0 <= 0;
+ repeat (1) @ (posedge clk);
+ #10 $finish;
+end
+
+// Connect the DUT
+arbiter U (
+ clk,
+ rst,
+ req3,
+ req2,
+ req1,
+ req0,
+ gnt3,
+ gnt2,
+ gnt1,
+ gnt0
+);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_cam.v b/tests/asicworld/code_hdl_models_cam.v
new file mode 100644
index 00000000..0cebc07c
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_cam.v
@@ -0,0 +1,60 @@
+//-----------------------------------------------------
+// Design Name : cam
+// File Name : cam.v
+// Function : CAM
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module cam (
+clk , // Cam clock
+cam_enable , // Cam enable
+cam_data_in , // Cam data to match
+cam_hit_out , // Cam match has happened
+cam_addr_out // Cam output address
+);
+
+parameter ADDR_WIDTH = 8;
+parameter DEPTH = 1 << ADDR_WIDTH;
+//------------Input Ports--------------
+input clk;
+input cam_enable;
+input [DEPTH-1:0] cam_data_in;
+//----------Output Ports--------------
+output cam_hit_out;
+output [ADDR_WIDTH-1:0] cam_addr_out;
+//------------Internal Variables--------
+reg [ADDR_WIDTH-1:0] cam_addr_out;
+reg cam_hit_out;
+reg [ADDR_WIDTH-1:0] cam_addr_combo;
+reg cam_hit_combo;
+reg found_match;
+integer i;
+//-------------Code Starts Here-------
+always @(cam_data_in) begin
+ cam_addr_combo = {ADDR_WIDTH{1'b0}};
+ found_match = 1'b0;
+ cam_hit_combo = 1'b0;
+ for (i=0; i<DEPTH; i=i+1) begin
+ if (cam_data_in[i] && !found_match) begin
+ found_match = 1'b1;
+ cam_hit_combo = 1'b1;
+ cam_addr_combo = i;
+ end else begin
+ found_match = found_match;
+ cam_hit_combo = cam_hit_combo;
+ cam_addr_combo = cam_addr_combo;
+ end
+ end
+end
+
+// Register the outputs
+always @(posedge clk) begin
+ if (cam_enable) begin
+ cam_hit_out <= cam_hit_combo;
+ cam_addr_out <= cam_addr_combo;
+ end else begin
+ cam_hit_out <= 1'b0;
+ cam_addr_out <= {ADDR_WIDTH{1'b0}};
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_clk_div.v b/tests/asicworld/code_hdl_models_clk_div.v
new file mode 100644
index 00000000..c48ab0dd
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_clk_div.v
@@ -0,0 +1,27 @@
+//-----------------------------------------------------
+// Design Name : clk_div
+// File Name : clk_div.v
+// Function : Divide by two counter
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+
+module clk_div (clk_in, enable,reset, clk_out);
+ // --------------Port Declaration-----------------------
+ input clk_in ;
+ input reset ;
+ input enable ;
+ output clk_out ;
+ //--------------Port data type declaration-------------
+ wire clk_in ;
+ wire enable ;
+//--------------Internal Registers----------------------
+reg clk_out ;
+//--------------Code Starts Here-----------------------
+always @ (posedge clk_in)
+if (reset) begin
+ clk_out <= 1'b0;
+end else if (enable) begin
+ clk_out <= !clk_out ;
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_clk_div_45.v b/tests/asicworld/code_hdl_models_clk_div_45.v
new file mode 100644
index 00000000..d9d28967
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_clk_div_45.v
@@ -0,0 +1,54 @@
+//-----------------------------------------------------
+// Design Name : clk_div_45
+// File Name : clk_div_45.v
+// Function : Divide by 4.5
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module clk_div_45 (
+clk_in, // Input Clock
+enable, // Enable is sync with falling edge of clk_in
+clk_out // Output Clock
+);
+
+// --------------Port Declaration-----------------------
+input clk_in ;
+input enable ;
+output clk_out ;
+
+//--------------Port data type declaration-------------
+wire clk_in ;
+wire enable ;
+wire clk_out ;
+
+//--------------Internal Registers----------------------
+reg [3:0] counter1 ;
+reg [3:0] counter2 ;
+reg toggle1 ;
+reg toggle2 ;
+
+//--------------Code Starts Here-----------------------
+always @ (posedge clk_in)
+if (enable == 1'b0) begin
+ counter1 <= 4'b0;
+ toggle1 <= 0;
+end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
+ counter1 <= 4'b0;
+ toggle1 <= ~toggle1;
+end else begin
+ counter1 <= counter1 + 1;
+end
+
+always @ (negedge clk_in)
+if (enable == 1'b0) begin
+ counter2 <= 4'b0;
+ toggle2 <= 0;
+end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin
+ counter2 <= 4'b0;
+ toggle2 <= ~toggle2;
+end else begin
+ counter2 <= counter2 + 1;
+end
+
+assign clk_out = (counter1 <3 && counter2 < 3) & enable;
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_d_ff_gates.v b/tests/asicworld/code_hdl_models_d_ff_gates.v
new file mode 100644
index 00000000..8706f154
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_d_ff_gates.v
@@ -0,0 +1,29 @@
+module d_ff_gates(d,clk,q,q_bar);
+input d,clk;
+output q, q_bar;
+
+wire n1,n2,n3,q_bar_n;
+wire cn,dn,n4,n5,n6;
+
+// First Latch
+not (n1,d);
+
+nand (n2,d,clk);
+nand (n3,n1,clk);
+
+nand (dn,q_bar_n,n2);
+nand (q_bar_n,dn,n3);
+
+// Second Latch
+not (cn,clk);
+
+not (n4,dn);
+
+nand (n5,dn,cn);
+nand (n6,n4,cn);
+
+nand (q,q_bar,n5);
+nand (q_bar,q,n6);
+
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_d_latch_gates.v b/tests/asicworld/code_hdl_models_d_latch_gates.v
new file mode 100644
index 00000000..3f5f6b2b
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_d_latch_gates.v
@@ -0,0 +1,15 @@
+module d_latch_gates(d,clk,q,q_bar);
+input d,clk;
+output q, q_bar;
+
+wire n1,n2,n3;
+
+not (n1,d);
+
+nand (n2,d,clk);
+nand (n3,n1,clk);
+
+nand (q,q_bar,n2);
+nand (q_bar,q,n3);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_decoder_2to4_gates.v b/tests/asicworld/code_hdl_models_decoder_2to4_gates.v
new file mode 100644
index 00000000..810003a8
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_decoder_2to4_gates.v
@@ -0,0 +1,14 @@
+module decoder_2to4_gates (x,y,f0,f1,f2,f3);
+input x,y;
+output f0,f1,f2,f3;
+
+wire n1,n2;
+
+not i1 (n1,x);
+not i2 (n2,y);
+and a1 (f0,n1,n2);
+and a2 (f1,n1,y);
+and a3 (f2,x,n2);
+and a4 (f3,x,y);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_decoder_using_assign.v b/tests/asicworld/code_hdl_models_decoder_using_assign.v
new file mode 100644
index 00000000..ec0dc95b
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_decoder_using_assign.v
@@ -0,0 +1,20 @@
+//-----------------------------------------------------
+// Design Name : decoder_using_assign
+// File Name : decoder_using_assign.v
+// Function : decoder using assign
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module decoder_using_assign (
+binary_in , // 4 bit binary input
+decoder_out , // 16-bit out
+enable // Enable for the decoder
+);
+input [3:0] binary_in ;
+input enable ;
+output [15:0] decoder_out ;
+
+wire [15:0] decoder_out ;
+
+assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_decoder_using_case.v b/tests/asicworld/code_hdl_models_decoder_using_case.v
new file mode 100644
index 00000000..ad42acdf
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_decoder_using_case.v
@@ -0,0 +1,43 @@
+//-----------------------------------------------------
+// Design Name : decoder_using_case
+// File Name : decoder_using_case.v
+// Function : decoder using case
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module decoder_using_case (
+binary_in , // 4 bit binary input
+decoder_out , // 16-bit out
+enable // Enable for the decoder
+);
+input [3:0] binary_in ;
+input enable ;
+output [15:0] decoder_out ;
+
+reg [15:0] decoder_out ;
+
+always @ (enable or binary_in)
+begin
+ decoder_out = 0;
+ if (enable) begin
+ case (binary_in)
+ 4'h0 : decoder_out = 16'h0001;
+ 4'h1 : decoder_out = 16'h0002;
+ 4'h2 : decoder_out = 16'h0004;
+ 4'h3 : decoder_out = 16'h0008;
+ 4'h4 : decoder_out = 16'h0010;
+ 4'h5 : decoder_out = 16'h0020;
+ 4'h6 : decoder_out = 16'h0040;
+ 4'h7 : decoder_out = 16'h0080;
+ 4'h8 : decoder_out = 16'h0100;
+ 4'h9 : decoder_out = 16'h0200;
+ 4'hA : decoder_out = 16'h0400;
+ 4'hB : decoder_out = 16'h0800;
+ 4'hC : decoder_out = 16'h1000;
+ 4'hD : decoder_out = 16'h2000;
+ 4'hE : decoder_out = 16'h4000;
+ 4'hF : decoder_out = 16'h8000;
+ endcase
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_dff_async_reset.v b/tests/asicworld/code_hdl_models_dff_async_reset.v
new file mode 100644
index 00000000..a156082f
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_dff_async_reset.v
@@ -0,0 +1,30 @@
+//-----------------------------------------------------
+// Design Name : dff_async_reset
+// File Name : dff_async_reset.v
+// Function : D flip-flop async reset
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module dff_async_reset (
+data , // Data Input
+clk , // Clock Input
+reset , // Reset input
+q // Q output
+);
+//-----------Input Ports---------------
+input data, clk, reset ;
+
+//-----------Output Ports---------------
+output q;
+
+//------------Internal Variables--------
+reg q;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk or negedge reset)
+if (~reset) begin
+ q <= 1'b0;
+end else begin
+ q <= data;
+end
+
+endmodule //End Of Module dff_async_reset
diff --git a/tests/asicworld/code_hdl_models_dff_sync_reset.v b/tests/asicworld/code_hdl_models_dff_sync_reset.v
new file mode 100644
index 00000000..7ef40454
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_dff_sync_reset.v
@@ -0,0 +1,30 @@
+//-----------------------------------------------------
+// Design Name : dff_sync_reset
+// File Name : dff_sync_reset.v
+// Function : D flip-flop sync reset
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module dff_sync_reset (
+data , // Data Input
+clk , // Clock Input
+reset , // Reset input
+q // Q output
+);
+//-----------Input Ports---------------
+input data, clk, reset ;
+
+//-----------Output Ports---------------
+output q;
+
+//------------Internal Variables--------
+reg q;
+
+//-------------Code Starts Here---------
+always @ ( posedge clk)
+if (~reset) begin
+ q <= 1'b0;
+end else begin
+ q <= data;
+end
+
+endmodule //End Of Module dff_sync_reset
diff --git a/tests/asicworld/code_hdl_models_dlatch_reset.v b/tests/asicworld/code_hdl_models_dlatch_reset.v
new file mode 100644
index 00000000..2cfc6fbd
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_dlatch_reset.v
@@ -0,0 +1,30 @@
+//-----------------------------------------------------
+// Design Name : dlatch_reset
+// File Name : dlatch_reset.v
+// Function : DLATCH async reset
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module dlatch_reset (
+data , // Data Input
+en , // LatchInput
+reset , // Reset input
+q // Q output
+);
+//-----------Input Ports---------------
+input data, en, reset ;
+
+//-----------Output Ports---------------
+output q;
+
+//------------Internal Variables--------
+reg q;
+
+//-------------Code Starts Here---------
+always @ ( en or reset or data)
+if (~reset) begin
+ q <= 1'b0;
+end else if (en) begin
+ q <= data;
+end
+
+endmodule //End Of Module dlatch_reset
diff --git a/tests/asicworld/code_hdl_models_encoder_4to2_gates.v b/tests/asicworld/code_hdl_models_encoder_4to2_gates.v
new file mode 100644
index 00000000..0bfdc28a
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_encoder_4to2_gates.v
@@ -0,0 +1,8 @@
+module encoder_4to2_gates (i0,i1,i2,i3,y);
+input i0,i1,i2,i3;
+output [1:0] y;
+
+or o1 (y[0],i1,i3);
+or o2 (y[1],i2,i3);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_encoder_using_case.v b/tests/asicworld/code_hdl_models_encoder_using_case.v
new file mode 100644
index 00000000..32e1b720
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_encoder_using_case.v
@@ -0,0 +1,42 @@
+//-----------------------------------------------------
+// Design Name : encoder_using_case
+// File Name : encoder_using_case.v
+// Function : Encoder using Case
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module encoder_using_case(
+binary_out , // 4 bit binary Output
+encoder_in , // 16-bit Input
+enable // Enable for the encoder
+);
+output [3:0] binary_out ;
+input enable ;
+input [15:0] encoder_in ;
+
+reg [3:0] binary_out ;
+
+always @ (enable or encoder_in)
+begin
+ binary_out = 0;
+ if (enable) begin
+ case (encoder_in)
+ 16'h0002 : binary_out = 1;
+ 16'h0004 : binary_out = 2;
+ 16'h0008 : binary_out = 3;
+ 16'h0010 : binary_out = 4;
+ 16'h0020 : binary_out = 5;
+ 16'h0040 : binary_out = 6;
+ 16'h0080 : binary_out = 7;
+ 16'h0100 : binary_out = 8;
+ 16'h0200 : binary_out = 9;
+ 16'h0400 : binary_out = 10;
+ 16'h0800 : binary_out = 11;
+ 16'h1000 : binary_out = 12;
+ 16'h2000 : binary_out = 13;
+ 16'h4000 : binary_out = 14;
+ 16'h8000 : binary_out = 15;
+ endcase
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_encoder_using_if.v b/tests/asicworld/code_hdl_models_encoder_using_if.v
new file mode 100644
index 00000000..2c97ddba
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_encoder_using_if.v
@@ -0,0 +1,58 @@
+//-----------------------------------------------------
+// Design Name : encoder_using_if
+// File Name : encoder_using_if.v
+// Function : Encoder using If
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module encoder_using_if(
+binary_out , // 4 bit binary output
+encoder_in , // 16-bit input
+enable // Enable for the encoder
+);
+//-----------Output Ports---------------
+output [3:0] binary_out ;
+//-----------Input Ports---------------
+input enable ;
+input [15:0] encoder_in ;
+//------------Internal Variables--------
+reg [3:0] binary_out ;
+//-------------Code Start-----------------
+always @ (enable or encoder_in)
+ begin
+ binary_out = 0;
+ if (enable) begin
+ if (encoder_in == 16'h0002) begin
+ binary_out = 1;
+ end if (encoder_in == 16'h0004) begin
+ binary_out = 2;
+ end if (encoder_in == 16'h0008) begin
+ binary_out = 3;
+ end if (encoder_in == 16'h0010) begin
+ binary_out = 4;
+ end if (encoder_in == 16'h0020) begin
+ binary_out = 5;
+ end if (encoder_in == 16'h0040) begin
+ binary_out = 6;
+ end if (encoder_in == 16'h0080) begin
+ binary_out = 7;
+ end if (encoder_in == 16'h0100) begin
+ binary_out = 8;
+ end if (encoder_in == 16'h0200) begin
+ binary_out = 9;
+ end if (encoder_in == 16'h0400) begin
+ binary_out = 10;
+ end if (encoder_in == 16'h0800) begin
+ binary_out = 11;
+ end if (encoder_in == 16'h1000) begin
+ binary_out = 12;
+ end if (encoder_in == 16'h2000) begin
+ binary_out = 13;
+ end if (encoder_in == 16'h4000) begin
+ binary_out = 14;
+ end if (encoder_in == 16'h8000) begin
+ binary_out = 15;
+ end
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_full_adder_gates.v b/tests/asicworld/code_hdl_models_full_adder_gates.v
new file mode 100644
index 00000000..1ddc4c56
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_full_adder_gates.v
@@ -0,0 +1,18 @@
+//-----------------------------------------------------
+// Design Name : full_adder_gates
+// File Name : full_adder_gates.v
+// Function : Full Adder Using Gates
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module full_adder_gates(x,y,z,sum,carry);
+input x,y,z;
+output sum,carry;
+wire and1,and2,and3,sum1;
+
+and U_and1 (and1,x,y),
+ U_and2 (and2,x,z),
+ U_and3 (and3,y,z);
+or U_or (carry,and1,and2,and3);
+xor U_sum (sum,x,y,z);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_full_subtracter_gates.v b/tests/asicworld/code_hdl_models_full_subtracter_gates.v
new file mode 100644
index 00000000..c24588ec
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_full_subtracter_gates.v
@@ -0,0 +1,20 @@
+//-----------------------------------------------------
+// Design Name : full_subtracter_gates
+// File Name : full_subtracter_gates.v
+// Function : Full Subtracter Using Gates
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module full_subtracter_gates(x,y,z,difference,borrow);
+input x,y,z;
+output difference,borrow;
+
+wire inv_x,borrow1,borrow2,borrow3;
+
+not (inv_x,x);
+and U_borrow1 (borrow1,inv_x,y),
+ U_borrow2 (borrow2,inv_x,z),
+ U_borrow3 (borrow3,y,z);
+
+xor U_diff (difference,borrow1,borrow2,borrows);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_gray_counter.v b/tests/asicworld/code_hdl_models_gray_counter.v
new file mode 100644
index 00000000..bc1e740a
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_gray_counter.v
@@ -0,0 +1,33 @@
+//-----------------------------------------------------
+// Design Name : gray_counter
+// File Name : gray_counter.v
+// Function : 8 bit gray counterS
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module gray_counter (
+ out , // counter out
+ enable , // enable for counter
+ clk , // clock
+ rst // active hight reset
+ );
+
+ //------------Input Ports--------------
+ input clk, rst, enable;
+ //----------Output Ports----------------
+ output [ 7:0] out;
+ //------------Internal Variables--------
+ wire [7:0] out;
+ reg [7:0] count;
+ //-------------Code Starts Here---------
+ always @ (posedge clk)
+ if (rst)
+ count <= 0;
+ else if (enable)
+ count <= count + 1;
+
+ assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
+ count[5]),(count[5] ^ count[4]), (count[4] ^
+ count[3]),(count[3] ^ count[2]), (count[2] ^
+ count[1]),(count[1] ^ count[0]) };
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_half_adder_gates.v b/tests/asicworld/code_hdl_models_half_adder_gates.v
new file mode 100644
index 00000000..6acf243f
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_half_adder_gates.v
@@ -0,0 +1,14 @@
+//-----------------------------------------------------
+// Design Name : half_adder_gates
+// File Name : half_adder_gates.v
+// Function : CCITT Serial CRC
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module half_adder_gates(x,y,sum,carry);
+input x,y;
+output sum,carry;
+
+and U_carry (carry,x,y);
+xor U_sum (sum,x,y);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_lfsr.v b/tests/asicworld/code_hdl_models_lfsr.v
new file mode 100644
index 00000000..63978083
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_lfsr.v
@@ -0,0 +1,35 @@
+//-----------------------------------------------------
+// Design Name : lfsr
+// File Name : lfsr.v
+// Function : Linear feedback shift register
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module lfsr (
+out , // Output of the counter
+enable , // Enable for counter
+clk , // clock input
+reset // reset input
+);
+
+//----------Output Ports--------------
+output [7:0] out;
+//------------Input Ports--------------
+input enable, clk, reset;
+//------------Internal Variables--------
+reg [7:0] out;
+wire linear_feedback;
+
+//-------------Code Starts Here-------
+assign linear_feedback = !(out[7] ^ out[3]);
+
+always @(posedge clk)
+if (reset) begin // active high reset
+ out <= 8'b0 ;
+end else if (enable) begin
+ out <= {out[6],out[5],
+ out[4],out[3],
+ out[2],out[1],
+ out[0], linear_feedback};
+end
+
+endmodule // End Of Module counter
diff --git a/tests/asicworld/code_hdl_models_lfsr_updown.v b/tests/asicworld/code_hdl_models_lfsr_updown.v
new file mode 100644
index 00000000..0bd29b83
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_lfsr_updown.v
@@ -0,0 +1,35 @@
+`define WIDTH 8
+module lfsr_updown (
+clk , // Clock input
+reset , // Reset input
+enable , // Enable input
+up_down , // Up Down input
+count , // Count output
+overflow // Overflow output
+);
+
+ input clk;
+ input reset;
+ input enable;
+ input up_down;
+
+ output [`WIDTH-1 : 0] count;
+ output overflow;
+
+ reg [`WIDTH-1 : 0] count;
+
+ assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) :
+ (count == {1'b1, {`WIDTH-1{1'b0}}}) ;
+
+ always @(posedge clk)
+ if (reset)
+ count <= {`WIDTH{1'b0}};
+ else if (enable) begin
+ if (up_down) begin
+ count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};
+ end else begin
+ count <= {count[`WIDTH-2:0],~(^(count & `WIDTH'b10110001))};
+ end
+ end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v
new file mode 100644
index 00000000..e3d9d5d6
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_misc1.v
@@ -0,0 +1,22 @@
+module misc1 (a,b,c,d,y);
+input a, b,c,d;
+output y;
+
+wire net1,net2,net3;
+
+supply1 vdd;
+supply0 vss;
+
+// y = !((a+b+c).d)
+
+pmos p1 (vdd,net1,a);
+pmos p2 (net1,net2,b);
+pmos p3 (net2,y,c);
+pmos p4 (vdd,y,d);
+
+nmos n1 (vss,net3,a);
+nmos n2 (vss,net3,b);
+nmos n3 (vss,net3,c);
+nmos n4 (net3,y,d);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v
new file mode 100644
index 00000000..519c07fc
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_mux21_switch.v
@@ -0,0 +1,22 @@
+//-----------------------------------------------------
+// Design Name : mux21_switch
+// File Name : mux21_switch.v
+// Function : 2:1 Mux using Switch Primitives
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module mux21_switch (out, ctrl, in1, in2);
+
+ output out;
+ input ctrl, in1, in2;
+ wire w;
+
+ supply1 power;
+ supply0 ground;
+
+ pmos N1 (w, power, ctrl);
+ nmos N2 (w, ground, ctrl);
+
+ cmos C1 (out, in1, w, ctrl);
+ cmos C2 (out, in2, ctrl, w);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_mux_2to1_gates.v b/tests/asicworld/code_hdl_models_mux_2to1_gates.v
new file mode 100644
index 00000000..fc762159
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_mux_2to1_gates.v
@@ -0,0 +1,18 @@
+//-----------------------------------------------------
+// Design Name : mux_2to1_gates
+// File Name : mux_2to1_gates.v
+// Function : 2:1 Mux using Gate Primitives
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module mux_2to1_gates(a,b,sel,y);
+input a,b,sel;
+output y;
+
+wire sel,a_sel,b_sel;
+
+not U_inv (inv_sel,sel);
+and U_anda (asel,a,inv_sel),
+ U_andb (bsel,b,sel);
+or U_or (y,asel,bsel);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_mux_using_assign.v b/tests/asicworld/code_hdl_models_mux_using_assign.v
new file mode 100644
index 00000000..4284f10c
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_mux_using_assign.v
@@ -0,0 +1,22 @@
+//-----------------------------------------------------
+// Design Name : mux_using_assign
+// File Name : mux_using_assign.v
+// Function : 2:1 Mux using Assign
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module mux_using_assign(
+din_0 , // Mux first input
+din_1 , // Mux Second input
+sel , // Select input
+mux_out // Mux output
+);
+//-----------Input Ports---------------
+input din_0, din_1, sel ;
+//-----------Output Ports---------------
+output mux_out;
+//------------Internal Variables--------
+wire mux_out;
+//-------------Code Start-----------------
+assign mux_out = (sel) ? din_1 : din_0;
+
+endmodule //End Of Module mux
diff --git a/tests/asicworld/code_hdl_models_mux_using_case.v b/tests/asicworld/code_hdl_models_mux_using_case.v
new file mode 100644
index 00000000..123da448
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_mux_using_case.v
@@ -0,0 +1,28 @@
+//-----------------------------------------------------
+// Design Name : mux_using_case
+// File Name : mux_using_case.v
+// Function : 2:1 Mux using Case
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module mux_using_case(
+din_0 , // Mux first input
+din_1 , // Mux Second input
+sel , // Select input
+mux_out // Mux output
+);
+//-----------Input Ports---------------
+input din_0, din_1, sel ;
+//-----------Output Ports---------------
+output mux_out;
+//------------Internal Variables--------
+reg mux_out;
+//-------------Code Starts Here---------
+always @ (sel or din_0 or din_1)
+begin : MUX
+ case(sel )
+ 1'b0 : mux_out = din_0;
+ 1'b1 : mux_out = din_1;
+ endcase
+end
+
+endmodule //End Of Module mux
diff --git a/tests/asicworld/code_hdl_models_mux_using_if.v b/tests/asicworld/code_hdl_models_mux_using_if.v
new file mode 100644
index 00000000..4d42e208
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_mux_using_if.v
@@ -0,0 +1,29 @@
+//-----------------------------------------------------
+// Design Name : mux_using_if
+// File Name : mux_using_if.v
+// Function : 2:1 Mux using If
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module mux_using_if(
+din_0 , // Mux first input
+din_1 , // Mux Second input
+sel , // Select input
+mux_out // Mux output
+);
+//-----------Input Ports---------------
+input din_0, din_1, sel ;
+//-----------Output Ports---------------
+output mux_out;
+//------------Internal Variables--------
+reg mux_out;
+//-------------Code Starts Here---------
+always @ (sel or din_0 or din_1)
+begin : MUX
+ if (sel == 1'b0) begin
+ mux_out = din_0;
+ end else begin
+ mux_out = din_1 ;
+ end
+end
+
+endmodule //End Of Module mux
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v
new file mode 100644
index 00000000..1ccdd3a7
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_nand_switch.v
@@ -0,0 +1,14 @@
+module nand_switch(a,b,out);
+input a,b;
+output out;
+
+supply0 vss;
+supply1 vdd;
+wire net1;
+
+pmos p1 (vdd,out,a);
+pmos p2 (vdd,out,b);
+nmos n1 (vss,net1,a);
+nmos n2 (net1,out,b);
+
+endmodule \ No newline at end of file
diff --git a/tests/asicworld/code_hdl_models_one_hot_cnt.v b/tests/asicworld/code_hdl_models_one_hot_cnt.v
new file mode 100644
index 00000000..f6b84c6e
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_one_hot_cnt.v
@@ -0,0 +1,31 @@
+//-----------------------------------------------------
+// Design Name : one_hot_cnt
+// File Name : one_hot_cnt.v
+// Function : 8 bit one hot counter
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module one_hot_cnt (
+out , // Output of the counter
+enable , // enable for counter
+clk , // clock input
+reset // reset input
+);
+//----------Output Ports--------------
+output [7:0] out;
+
+//------------Input Ports--------------
+input enable, clk, reset;
+
+//------------Internal Variables--------
+reg [7:0] out;
+
+//-------------Code Starts Here-------
+always @ (posedge clk)
+if (reset) begin
+ out <= 8'b0000_0001 ;
+end else if (enable) begin
+ out <= {out[6],out[5],out[4],out[3],
+ out[2],out[1],out[0],out[7]};
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_parallel_crc.v b/tests/asicworld/code_hdl_models_parallel_crc.v
new file mode 100644
index 00000000..d8d0bf1c
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_parallel_crc.v
@@ -0,0 +1,53 @@
+//-----------------------------------------------------
+// Design Name : parallel_crc_ccitt
+// File Name : parallel_crc.v
+// Function : CCITT Parallel CRC
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module parallel_crc_ccitt (
+clk ,
+reset ,
+enable ,
+init ,
+data_in ,
+crc_out
+);
+//-----------Input Ports---------------
+input clk ;
+input reset ;
+input enable ;
+input init ;
+input [7:0] data_in ;
+//-----------Output Ports---------------
+output [15:0] crc_out;
+//------------Internal Variables--------
+reg [15:0] crc_reg;
+wire [15:0] next_crc;
+//-------------Code Start-----------------
+assign crc_out = crc_reg;
+// CRC Control logic
+always @ (posedge clk)
+if (reset) begin
+ crc_reg <= 16'hFFFF;
+end else if (enable) begin
+ if (init) begin
+ crc_reg <= 16'hFFFF;
+ end else begin
+ crc_reg <= next_crc;
+ end
+end
+// Parallel CRC calculation
+assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
+assign next_crc[1] = data_in[1] ^ crc_reg[5];
+assign next_crc[2] = data_in[2] ^ crc_reg[6];
+assign next_crc[3] = data_in[3] ^ crc_reg[7];
+assign next_crc[4] = data_in[4] ^ crc_reg[8];
+assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
+assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];
+assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];
+assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
+assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];
+assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];
+assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_parity_using_assign.v b/tests/asicworld/code_hdl_models_parity_using_assign.v
new file mode 100644
index 00000000..b0282e8d
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_parity_using_assign.v
@@ -0,0 +1,21 @@
+//-----------------------------------------------------
+// Design Name : parity_using_assign
+// File Name : parity_using_assign.v
+// Function : Parity using assign
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module parity_using_assign (
+data_in , // 8 bit data in
+parity_out // 1 bit parity out
+);
+output parity_out ;
+input [7:0] data_in ;
+
+wire parity_out ;
+
+assign parity_out = (data_in[0] ^ data_in[1]) ^
+ (data_in[2] ^ data_in[3]) ^
+ (data_in[4] ^ data_in[5]) ^
+ (data_in[6] ^ data_in[7]);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_parity_using_bitwise.v b/tests/asicworld/code_hdl_models_parity_using_bitwise.v
new file mode 100644
index 00000000..0046fb14
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_parity_using_bitwise.v
@@ -0,0 +1,16 @@
+//-----------------------------------------------------
+// Design Name : parity_using_bitwise
+// File Name : parity_using_bitwise.v
+// Function : Parity using bitwise xor
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module parity_using_bitwise (
+data_in , // 8 bit data in
+parity_out // 1 bit parity out
+);
+output parity_out ;
+input [7:0] data_in ;
+
+assign parity_out = ^data_in;
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_parity_using_function.v b/tests/asicworld/code_hdl_models_parity_using_function.v
new file mode 100644
index 00000000..0d07aaeb
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_parity_using_function.v
@@ -0,0 +1,29 @@
+//-----------------------------------------------------
+// Design Name : parity_using_function
+// File Name : parity_using_function.v
+// Function : Parity using function
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module parity_using_function (
+data_in , // 8 bit data in
+parity_out // 1 bit parity out
+);
+output parity_out ;
+input [7:0] data_in ;
+
+wire parity_out ;
+
+function parity;
+ input [31:0] data;
+ begin
+ parity = (data_in[0] ^ data_in[1]) ^
+ (data_in[2] ^ data_in[3]) ^
+ (data_in[4] ^ data_in[5]) ^
+ (data_in[6] ^ data_in[7]);
+ end
+endfunction
+
+
+assign parity_out = parity(data_in);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v
new file mode 100644
index 00000000..c1ce960c
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v
@@ -0,0 +1,36 @@
+//-----------------------------------------------------
+// Design Name : pri_encoder_using_assign
+// File Name : pri_encoder_using_assign.v
+// Function : Pri Encoder using assign
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module pri_encoder_using_assign (
+binary_out , // 4 bit binary output
+encoder_in , // 16-bit input
+enable // Enable for the encoder
+);
+
+output [3:0] binary_out ;
+input enable ;
+input [15:0] encoder_in ;
+
+wire [3:0] binary_out ;
+
+assign binary_out = (!enable) ? 0 : (
+ (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
+ (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
+ (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
+ (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
+ (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
+ (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
+ (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
+ (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
+ (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
+ (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
+ (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
+ (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
+ (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
+ (encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
+ (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v b/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v
new file mode 100644
index 00000000..d3338f74
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_ram_sp_ar_sw.v
@@ -0,0 +1,58 @@
+//-----------------------------------------------------
+// Design Name : ram_sp_ar_sw
+// File Name : ram_sp_ar_sw.v
+// Function : Asynchronous read write RAM
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module ram_sp_ar_sw (
+clk , // Clock Input
+address , // Address Input
+data , // Data bi-directional
+cs , // Chip Select
+we , // Write Enable/Read Enable
+oe // Output Enable
+);
+
+parameter DATA_WIDTH = 8 ;
+parameter ADDR_WIDTH = 8 ;
+parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+
+//--------------Input Ports-----------------------
+input clk ;
+input [ADDR_WIDTH-1:0] address ;
+input cs ;
+input we ;
+input oe ;
+
+//--------------Inout Ports-----------------------
+inout [DATA_WIDTH-1:0] data ;
+
+//--------------Internal variables----------------
+reg [DATA_WIDTH-1:0] data_out ;
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+//--------------Code Starts Here------------------
+
+// Tri-State Buffer control
+// output : When we = 0, oe = 1, cs = 1
+assign data = (cs && oe && !we) ? data_out : 8'bz;
+
+// Memory Write Block
+// Write Operation : When we = 1, cs = 1
+always @ (posedge clk)
+begin : MEM_WRITE
+ if ( cs && we ) begin
+ mem[address] = data;
+ end
+end
+
+// Memory Read Block
+// Read Operation : When we = 0, oe = 1, cs = 1
+always @ (address or cs or we or oe)
+begin : MEM_READ
+ if (cs && !we && oe) begin
+ data_out = mem[address];
+ end
+end
+
+endmodule // End of Module ram_sp_ar_sw
diff --git a/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v b/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v
new file mode 100644
index 00000000..c7fd9554
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_ram_sp_sr_sw.v
@@ -0,0 +1,62 @@
+//-----------------------------------------------------
+// Design Name : ram_sp_sr_sw
+// File Name : ram_sp_sr_sw.v
+// Function : Synchronous read write RAM
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module ram_sp_sr_sw (
+clk , // Clock Input
+address , // Address Input
+data , // Data bi-directional
+cs , // Chip Select
+we , // Write Enable/Read Enable
+oe // Output Enable
+);
+
+parameter DATA_WIDTH = 8 ;
+parameter ADDR_WIDTH = 8 ;
+parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+
+//--------------Input Ports-----------------------
+input clk ;
+input [ADDR_WIDTH-1:0] address ;
+input cs ;
+input we ;
+input oe ;
+
+//--------------Inout Ports-----------------------
+inout [DATA_WIDTH-1:0] data ;
+
+//--------------Internal variables----------------
+reg [DATA_WIDTH-1:0] data_out ;
+reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+reg oe_r;
+
+//--------------Code Starts Here------------------
+
+// Tri-State Buffer control
+// output : When we = 0, oe = 1, cs = 1
+assign data = (cs && oe && !we) ? data_out : 8'bz;
+
+// Memory Write Block
+// Write Operation : When we = 1, cs = 1
+always @ (posedge clk)
+begin : MEM_WRITE
+ if ( cs && we ) begin
+ mem[address] = data;
+ end
+end
+
+// Memory Read Block
+// Read Operation : When we = 0, oe = 1, cs = 1
+always @ (posedge clk)
+begin : MEM_READ
+ if (cs && !we && oe) begin
+ data_out = mem[address];
+ oe_r = 1;
+ end else begin
+ oe_r = 0;
+ end
+end
+
+endmodule // End of Module ram_sp_sr_sw
diff --git a/tests/asicworld/code_hdl_models_rom_using_case.v b/tests/asicworld/code_hdl_models_rom_using_case.v
new file mode 100644
index 00000000..6b700993
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_rom_using_case.v
@@ -0,0 +1,42 @@
+//-----------------------------------------------------
+// Design Name : rom_using_case
+// File Name : rom_using_case.v
+// Function : ROM using case
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module rom_using_case (
+address , // Address input
+data , // Data output
+read_en , // Read Enable
+ce // Chip Enable
+);
+input [3:0] address;
+output [7:0] data;
+input read_en;
+input ce;
+
+reg [7:0] data ;
+
+always @ (ce or read_en or address)
+begin
+ case (address)
+ 0 : data = 10;
+ 1 : data = 55;
+ 2 : data = 244;
+ 3 : data = 0;
+ 4 : data = 1;
+ 5 : data = 8'hff;
+ 6 : data = 8'h11;
+ 7 : data = 8'h1;
+ 8 : data = 8'h10;
+ 9 : data = 8'h0;
+ 10 : data = 8'h10;
+ 11 : data = 8'h15;
+ 12 : data = 8'h60;
+ 13 : data = 8'h90;
+ 14 : data = 8'h70;
+ 15 : data = 8'h90;
+ endcase
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_serial_crc.v b/tests/asicworld/code_hdl_models_serial_crc.v
new file mode 100644
index 00000000..a4a63a26
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_serial_crc.v
@@ -0,0 +1,54 @@
+//-----------------------------------------------------
+// Design Name : serial_crc_ccitt
+// File Name : serial_crc.v
+// Function : CCITT Serial CRC
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module serial_crc_ccitt (
+clk ,
+reset ,
+enable ,
+init ,
+data_in ,
+crc_out
+);
+//-----------Input Ports---------------
+input clk ;
+input reset ;
+input enable ;
+input init ;
+input data_in ;
+//-----------Output Ports---------------
+output [15:0] crc_out;
+//------------Internal Variables--------
+reg [15:0] lfsr;
+//-------------Code Start-----------------
+assign crc_out = lfsr;
+// Logic to CRC Calculation
+always @ (posedge clk)
+if (reset) begin
+ lfsr <= 16'hFFFF;
+end else if (enable) begin
+ if (init) begin
+ lfsr <= 16'hFFFF;
+ end else begin
+ lfsr[0] <= data_in ^ lfsr[15];
+ lfsr[1] <= lfsr[0];
+ lfsr[2] <= lfsr[1];
+ lfsr[3] <= lfsr[2];
+ lfsr[4] <= lfsr[3];
+ lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];
+ lfsr[6] <= lfsr[5];
+ lfsr[7] <= lfsr[6];
+ lfsr[8] <= lfsr[7];
+ lfsr[9] <= lfsr[8];
+ lfsr[10] <= lfsr[9];
+ lfsr[11] <= lfsr[10];
+ lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
+ lfsr[13] <= lfsr[12];
+ lfsr[14] <= lfsr[13];
+ lfsr[15] <= lfsr[14];
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v
new file mode 100644
index 00000000..1bff66af
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_t_gate_switch.v
@@ -0,0 +1,11 @@
+module t_gate_switch (L,R,nC,C);
+ inout L;
+ inout R;
+ input nC;
+ input C;
+
+ //Syntax: keyword unique_name (drain. source, gate);
+ pmos p1 (L,R,nC);
+ nmos p2 (L,R,C);
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_tff_async_reset.v b/tests/asicworld/code_hdl_models_tff_async_reset.v
new file mode 100644
index 00000000..4c5a1fa9
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_tff_async_reset.v
@@ -0,0 +1,27 @@
+//-----------------------------------------------------
+// Design Name : tff_async_reset
+// File Name : tff_async_reset.v
+// Function : T flip-flop async reset
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module tff_async_reset (
+data , // Data Input
+clk , // Clock Input
+reset , // Reset input
+q // Q output
+);
+//-----------Input Ports---------------
+input data, clk, reset ;
+//-----------Output Ports---------------
+output q;
+//------------Internal Variables--------
+reg q;
+//-------------Code Starts Here---------
+always @ ( posedge clk or negedge reset)
+if (~reset) begin
+ q <= 1'b0;
+end else if (data) begin
+ q <= !q;
+end
+
+endmodule //End Of Module tff_async_reset
diff --git a/tests/asicworld/code_hdl_models_tff_sync_reset.v b/tests/asicworld/code_hdl_models_tff_sync_reset.v
new file mode 100644
index 00000000..a962d53d
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_tff_sync_reset.v
@@ -0,0 +1,27 @@
+//-----------------------------------------------------
+// Design Name : tff_sync_reset
+// File Name : tff_sync_reset.v
+// Function : T flip-flop sync reset
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module tff_sync_reset (
+data , // Data Input
+clk , // Clock Input
+reset , // Reset input
+q // Q output
+);
+//-----------Input Ports---------------
+input data, clk, reset ;
+//-----------Output Ports---------------
+output q;
+//------------Internal Variables--------
+reg q;
+//-------------Code Starts Here---------
+always @ ( posedge clk)
+if (~reset) begin
+ q <= 1'b0;
+end else if (data) begin
+ q <= !q;
+end
+
+endmodule //End Of Module tff_async_reset
diff --git a/tests/asicworld/code_hdl_models_uart.v b/tests/asicworld/code_hdl_models_uart.v
new file mode 100644
index 00000000..40205250
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_uart.v
@@ -0,0 +1,154 @@
+//-----------------------------------------------------
+// Design Name : uart
+// File Name : uart.v
+// Function : Simple UART
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module uart (
+reset ,
+txclk ,
+ld_tx_data ,
+tx_data ,
+tx_enable ,
+tx_out ,
+tx_empty ,
+rxclk ,
+uld_rx_data ,
+rx_data ,
+rx_enable ,
+rx_in ,
+rx_empty
+);
+// Port declarations
+input reset ;
+input txclk ;
+input ld_tx_data ;
+input [7:0] tx_data ;
+input tx_enable ;
+output tx_out ;
+output tx_empty ;
+input rxclk ;
+input uld_rx_data ;
+output [7:0] rx_data ;
+input rx_enable ;
+input rx_in ;
+output rx_empty ;
+
+// Internal Variables
+reg [7:0] tx_reg ;
+reg tx_empty ;
+reg tx_over_run ;
+reg [3:0] tx_cnt ;
+reg tx_out ;
+reg [7:0] rx_reg ;
+reg [7:0] rx_data ;
+reg [3:0] rx_sample_cnt ;
+reg [3:0] rx_cnt ;
+reg rx_frame_err ;
+reg rx_over_run ;
+reg rx_empty ;
+reg rx_d1 ;
+reg rx_d2 ;
+reg rx_busy ;
+
+// UART RX Logic
+always @ (posedge rxclk or posedge reset)
+if (reset) begin
+ rx_reg <= 0;
+ rx_data <= 0;
+ rx_sample_cnt <= 0;
+ rx_cnt <= 0;
+ rx_frame_err <= 0;
+ rx_over_run <= 0;
+ rx_empty <= 1;
+ rx_d1 <= 1;
+ rx_d2 <= 1;
+ rx_busy <= 0;
+end else begin
+ // Synchronize the asynch signal
+ rx_d1 <= rx_in;
+ rx_d2 <= rx_d1;
+ // Uload the rx data
+ if (uld_rx_data) begin
+ rx_data <= rx_reg;
+ rx_empty <= 1;
+ end
+ // Receive data only when rx is enabled
+ if (rx_enable) begin
+ // Check if just received start of frame
+ if (!rx_busy && !rx_d2) begin
+ rx_busy <= 1;
+ rx_sample_cnt <= 1;
+ rx_cnt <= 0;
+ end
+ // Start of frame detected, Proceed with rest of data
+ if (rx_busy) begin
+ rx_sample_cnt <= rx_sample_cnt + 1;
+ // Logic to sample at middle of data
+ if (rx_sample_cnt == 7) begin
+ if ((rx_d2 == 1) && (rx_cnt == 0)) begin
+ rx_busy <= 0;
+ end else begin
+ rx_cnt <= rx_cnt + 1;
+ // Start storing the rx data
+ if (rx_cnt > 0 && rx_cnt < 9) begin
+ rx_reg[rx_cnt - 1] <= rx_d2;
+ end
+ if (rx_cnt == 9) begin
+ rx_busy <= 0;
+ // Check if End of frame received correctly
+ if (rx_d2 == 0) begin
+ rx_frame_err <= 1;
+ end else begin
+ rx_empty <= 0;
+ rx_frame_err <= 0;
+ // Check if last rx data was not unloaded,
+ rx_over_run <= (rx_empty) ? 0 : 1;
+ end
+ end
+ end
+ end
+ end
+ end
+ if (!rx_enable) begin
+ rx_busy <= 0;
+ end
+end
+
+// UART TX Logic
+always @ (posedge txclk or posedge reset)
+if (reset) begin
+ tx_reg <= 0;
+ tx_empty <= 1;
+ tx_over_run <= 0;
+ tx_out <= 1;
+ tx_cnt <= 0;
+end else begin
+ if (ld_tx_data) begin
+ if (!tx_empty) begin
+ tx_over_run <= 0;
+ end else begin
+ tx_reg <= tx_data;
+ tx_empty <= 0;
+ end
+ end
+ if (tx_enable && !tx_empty) begin
+ tx_cnt <= tx_cnt + 1;
+ if (tx_cnt == 0) begin
+ tx_out <= 0;
+ end
+ if (tx_cnt > 0 && tx_cnt < 9) begin
+ tx_out <= tx_reg[tx_cnt -1];
+ end
+ if (tx_cnt == 9) begin
+ tx_out <= 1;
+ tx_cnt <= 0;
+ tx_empty <= 1;
+ end
+ end
+ if (!tx_enable) begin
+ tx_cnt <= 0;
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v
new file mode 100644
index 00000000..ffe67099
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_up_counter.v
@@ -0,0 +1,29 @@
+//-----------------------------------------------------
+// Design Name : up_counter
+// File Name : up_counter.v
+// Function : Up counter
+// Coder  : Deepak
+//-----------------------------------------------------
+module up_counter (
+out , // Output of the counter
+enable , // enable for counter
+clk , // clock Input
+reset // reset Input
+);
+//----------Output Ports--------------
+ output [7:0] out;
+//------------Input Ports--------------
+ input enable, clk, reset;
+//------------Internal Variables--------
+ reg [7:0] out;
+//-------------Code Starts Here-------
+always @(posedge clk)
+if (reset) begin
+ out <= 8'b0 ;
+end else if (enable) begin
+ out <= out + 1;
+end
+
+
+endmodule
+
diff --git a/tests/asicworld/code_hdl_models_up_counter_load.v b/tests/asicworld/code_hdl_models_up_counter_load.v
new file mode 100644
index 00000000..92ad895a
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_up_counter_load.v
@@ -0,0 +1,32 @@
+//-----------------------------------------------------
+// Design Name : up_counter_load
+// File Name : up_counter_load.v
+// Function : Up counter with load
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module up_counter_load (
+out , // Output of the counter
+data , // Parallel load for the counter
+load , // Parallel load enable
+enable , // Enable counting
+clk , // clock input
+reset // reset input
+);
+//----------Output Ports--------------
+output [7:0] out;
+//------------Input Ports--------------
+input [7:0] data;
+input load, enable, clk, reset;
+//------------Internal Variables--------
+reg [7:0] out;
+//-------------Code Starts Here-------
+always @(posedge clk)
+if (reset) begin
+ out <= 8'b0 ;
+end else if (load) begin
+ out <= data;
+end else if (enable) begin
+ out <= out + 1;
+end
+
+endmodule
diff --git a/tests/asicworld/code_hdl_models_up_down_counter.v b/tests/asicworld/code_hdl_models_up_down_counter.v
new file mode 100644
index 00000000..fff2982a
--- /dev/null
+++ b/tests/asicworld/code_hdl_models_up_down_counter.v
@@ -0,0 +1,29 @@
+//-----------------------------------------------------
+// Design Name : up_down_counter
+// File Name : up_down_counter.v
+// Function : Up down counter
+// Coder : Deepak Kumar Tala
+//-----------------------------------------------------
+module up_down_counter (
+out , // Output of the counter
+up_down , // up_down control for counter
+clk , // clock input
+reset // reset input
+);
+//----------Output Ports--------------
+output [7:0] out;
+//------------Input Ports--------------
+input up_down, clk, reset;
+//------------Internal Variables--------
+reg [7:0] out;
+//-------------Code Starts Here-------
+always @(posedge clk)
+if (reset) begin // active high reset
+ out <= 8'b0 ;
+end else if (up_down) begin
+ out <= out + 1;
+end else begin
+ out <= out - 1;
+end
+
+endmodule
diff --git a/tests/asicworld/code_specman_switch_fabric.v b/tests/asicworld/code_specman_switch_fabric.v
new file mode 100644
index 00000000..1ac7ee70
--- /dev/null
+++ b/tests/asicworld/code_specman_switch_fabric.v
@@ -0,0 +1,82 @@
+module switch_fabric(
+ clk, reset, data_in0, data_in1, data_in2,
+ data_in3, data_in4, data_in5, data_in_valid0,
+ data_in_valid1, data_in_valid2, data_in_valid3,
+ data_in_valid4, data_in_valid5, data_out0,
+ data_out1, data_out2, data_out3, data_out4,
+ data_out5, data_out_ack0, data_out_ack1,
+ data_out_ack2, data_out_ack3, data_out_ack4,
+ data_out_ack5
+);
+
+input clk, reset;
+input [7:0] data_in0, data_in1, data_in2, data_in3;
+input [7:0] data_in4, data_in5;
+input data_in_valid0, data_in_valid1, data_in_valid2;
+input [7:0] data_in_valid3, data_in_valid4, data_in_valid5;
+output [7:0] data_out0, data_out1, data_out2, data_out3;
+output [7:0] data_out4, data_out5;
+output data_out_ack0, data_out_ack1, data_out_ack2;
+output [7:0] data_out_ack3, data_out_ack4, data_out_ack5;
+
+(* gentb_clock *)
+wire clk;
+
+switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
+ .data_in_valid(data_in_valid0), .data_out(data_out0),
+ .data_out_ack(data_out_ack0));
+
+switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
+ .data_in_valid(data_in_valid1), .data_out(data_out1),
+ .data_out_ack(data_out_ack1));
+
+switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
+ .data_in_valid(data_in_valid2), .data_out(data_out2), .
+ data_out_ack(data_out_ack2));
+
+switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
+ .data_in_valid(data_in_valid3), .data_out(data_out3),
+ .data_out_ack(data_out_ack3));
+
+switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
+ .data_in_valid(data_in_valid4), .data_out(data_out4),
+ .data_out_ack(data_out_ack4));
+
+switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
+ .data_in_valid(data_in_valid5), .data_out(data_out5),
+ .data_out_ack(data_out_ack5));
+
+endmodule
+
+module switch (
+ clk,
+ reset,
+ data_in,
+ data_in_valid,
+ data_out,
+ data_out_ack
+);
+
+input clk;
+input reset;
+input [7:0] data_in;
+input data_in_valid;
+output [7:0] data_out;
+output data_out_ack;
+
+reg [7:0] data_out;
+reg data_out_ack;
+
+always @ (posedge clk)
+if (reset) begin
+ data_out <= 0;
+ data_out_ack <= 0;
+end else if (data_in_valid) begin
+ data_out <= data_in;
+ data_out_ack <= 1;
+end else begin
+ data_out <= 0;
+ data_out_ack <= 0;
+end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_asyn_reset.v b/tests/asicworld/code_tidbits_asyn_reset.v
new file mode 100644
index 00000000..58e47c56
--- /dev/null
+++ b/tests/asicworld/code_tidbits_asyn_reset.v
@@ -0,0 +1,18 @@
+module asyn_reset(clk,reset,a,c);
+ input clk;
+ input reset;
+ input a;
+ output c;
+
+ wire clk;
+ wire reset;
+ wire a;
+ reg c;
+
+always @ (posedge clk or posedge reset)
+ if ( reset == 1'b1) begin
+ c <= 0;
+ end else begin
+ c <= a;
+ end
+endmodule
diff --git a/tests/asicworld/code_tidbits_blocking.v b/tests/asicworld/code_tidbits_blocking.v
new file mode 100644
index 00000000..e13b72cc
--- /dev/null
+++ b/tests/asicworld/code_tidbits_blocking.v
@@ -0,0 +1,17 @@
+module blocking (clk,a,c);
+input clk;
+input a;
+output c;
+
+wire clk;
+wire a;
+reg c;
+reg b;
+
+always @ (posedge clk )
+begin
+ b = a;
+ c = b;
+end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_fsm_using_always.v b/tests/asicworld/code_tidbits_fsm_using_always.v
new file mode 100644
index 00000000..8a8775b9
--- /dev/null
+++ b/tests/asicworld/code_tidbits_fsm_using_always.v
@@ -0,0 +1,91 @@
+//-----------------------------------------------------
+// This is FSM demo program using always block
+// Design Name : fsm_using_always
+// File Name : fsm_using_always.v
+//-----------------------------------------------------
+module fsm_using_always (
+clock , // clock
+reset , // Active high, syn reset
+req_0 , // Request 0
+req_1 , // Request 1
+gnt_0 , // Grant 0
+gnt_1
+);
+//-------------Input Ports-----------------------------
+input clock,reset,req_0,req_1;
+ //-------------Output Ports----------------------------
+output gnt_0,gnt_1;
+//-------------Input ports Data Type-------------------
+wire clock,reset,req_0,req_1;
+//-------------Output Ports Data Type------------------
+reg gnt_0,gnt_1;
+//-------------Internal Constants--------------------------
+parameter SIZE = 3 ;
+parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
+//-------------Internal Variables---------------------------
+reg [SIZE-1:0] state ;// Seq part of the FSM
+reg [SIZE-1:0] next_state ;// combo part of FSM
+//----------Code startes Here------------------------
+always @ (state or req_0 or req_1)
+begin : FSM_COMBO
+ next_state = 3'b000;
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ next_state = GNT0;
+ end else if (req_1 == 1'b1) begin
+ next_state= GNT1;
+ end else begin
+ next_state = IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ next_state = GNT0;
+ end else begin
+ next_state = IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ next_state = GNT1;
+ end else begin
+ next_state = IDLE;
+ end
+ default : next_state = IDLE;
+ endcase
+end
+//----------Seq Logic-----------------------------
+always @ (posedge clock)
+begin : FSM_SEQ
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ end else begin
+ state <= #1 next_state;
+ end
+end
+//----------Output Logic-----------------------------
+always @ (posedge clock)
+begin : OUTPUT_LOGIC
+if (reset == 1'b1) begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+end
+else begin
+ case(state)
+ IDLE : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+ end
+ GNT0 : begin
+ gnt_0 <= #1 1'b1;
+ gnt_1 <= #1 1'b0;
+ end
+ GNT1 : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b1;
+ end
+ default : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+ end
+ endcase
+end
+end // End Of Block OUTPUT_LOGIC
+
+endmodule // End of Module arbiter
diff --git a/tests/asicworld/code_tidbits_fsm_using_function.v b/tests/asicworld/code_tidbits_fsm_using_function.v
new file mode 100644
index 00000000..404498a0
--- /dev/null
+++ b/tests/asicworld/code_tidbits_fsm_using_function.v
@@ -0,0 +1,94 @@
+//-----------------------------------------------------
+// This is FSM demo program using function
+// Design Name : fsm_using_function
+// File Name : fsm_using_function.v
+//-----------------------------------------------------
+module fsm_using_function (
+clock , // clock
+reset , // Active high, syn reset
+req_0 , // Request 0
+req_1 , // Request 1
+gnt_0 , // Grant 0
+gnt_1
+);
+//-------------Input Ports-----------------------------
+input clock,reset,req_0,req_1;
+ //-------------Output Ports----------------------------
+output gnt_0,gnt_1;
+//-------------Input ports Data Type-------------------
+wire clock,reset,req_0,req_1;
+//-------------Output Ports Data Type------------------
+reg gnt_0,gnt_1;
+//-------------Internal Constants--------------------------
+parameter SIZE = 3 ;
+parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
+//-------------Internal Variables---------------------------
+reg [SIZE-1:0] state ;// Seq part of the FSM
+wire [SIZE-1:0] next_state ;// combo part of FSM
+//----------Code startes Here------------------------
+assign next_state = fsm_function(state, req_0, req_1);
+//----------Function for Combo Logic-----------------
+function [SIZE-1:0] fsm_function;
+ input [SIZE-1:0] state ;
+ input req_0 ;
+ input req_1 ;
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ fsm_function = GNT0;
+ end else if (req_1 == 1'b1) begin
+ fsm_function= GNT1;
+ end else begin
+ fsm_function = IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ fsm_function = GNT0;
+ end else begin
+ fsm_function = IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ fsm_function = GNT1;
+ end else begin
+ fsm_function = IDLE;
+ end
+ default : fsm_function = IDLE;
+ endcase
+endfunction
+//----------Seq Logic-----------------------------
+always @ (posedge clock)
+begin : FSM_SEQ
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ end else begin
+ state <= #1 next_state;
+ end
+end
+//----------Output Logic-----------------------------
+always @ (posedge clock)
+begin : OUTPUT_LOGIC
+if (reset == 1'b1) begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+end
+else begin
+ case(state)
+ IDLE : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+ end
+ GNT0 : begin
+ gnt_0 <= #1 1'b1;
+ gnt_1 <= #1 1'b0;
+ end
+ GNT1 : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b1;
+ end
+ default : begin
+ gnt_0 <= #1 1'b0;
+ gnt_1 <= #1 1'b0;
+ end
+ endcase
+end
+end // End Of Block OUTPUT_LOGIC
+
+endmodule // End of Module arbiter
diff --git a/tests/asicworld/code_tidbits_fsm_using_single_always.v b/tests/asicworld/code_tidbits_fsm_using_single_always.v
new file mode 100644
index 00000000..67cc0884
--- /dev/null
+++ b/tests/asicworld/code_tidbits_fsm_using_single_always.v
@@ -0,0 +1,63 @@
+//====================================================
+// This is FSM demo program using single always
+// for both seq and combo logic
+// Design Name : fsm_using_single_always
+// File Name : fsm_using_single_always.v
+//=====================================================
+module fsm_using_single_always (
+clock , // clock
+reset , // Active high, syn reset
+req_0 , // Request 0
+req_1 , // Request 1
+gnt_0 , // Grant 0
+gnt_1
+);
+//=============Input Ports=============================
+input clock,reset,req_0,req_1;
+ //=============Output Ports===========================
+output gnt_0,gnt_1;
+//=============Input ports Data Type===================
+wire clock,reset,req_0,req_1;
+//=============Output Ports Data Type==================
+reg gnt_0,gnt_1;
+//=============Internal Constants======================
+parameter SIZE = 3 ;
+parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
+//=============Internal Variables======================
+reg [SIZE-1:0] state ;// Seq part of the FSM
+reg [SIZE-1:0] next_state ;// combo part of FSM
+//==========Code startes Here==========================
+always @ (posedge clock)
+begin : FSM
+if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+end else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT1;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT1;
+ end else begin
+ gnt_1 <= 0;
+ state <= #1 IDLE;
+ end
+ default : state <= #1 IDLE;
+endcase
+end
+
+endmodule // End of Module arbiter
diff --git a/tests/asicworld/code_tidbits_nonblocking.v b/tests/asicworld/code_tidbits_nonblocking.v
new file mode 100644
index 00000000..4a0d365e
--- /dev/null
+++ b/tests/asicworld/code_tidbits_nonblocking.v
@@ -0,0 +1,17 @@
+module nonblocking (clk,a,c);
+input clk;
+input a;
+output c;
+
+wire clk;
+wire a;
+reg c;
+reg b;
+
+always @ (posedge clk )
+begin
+ b <= a;
+ c <= b;
+end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_reg_combo_example.v b/tests/asicworld/code_tidbits_reg_combo_example.v
new file mode 100644
index 00000000..9689788c
--- /dev/null
+++ b/tests/asicworld/code_tidbits_reg_combo_example.v
@@ -0,0 +1,13 @@
+module reg_combo_example( a, b, y);
+input a, b;
+output y;
+
+reg y;
+wire a, b;
+
+always @ ( a or b)
+begin
+ y = a & b;
+end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_reg_seq_example.v b/tests/asicworld/code_tidbits_reg_seq_example.v
new file mode 100644
index 00000000..458c8792
--- /dev/null
+++ b/tests/asicworld/code_tidbits_reg_seq_example.v
@@ -0,0 +1,15 @@
+module reg_seq_example( clk, reset, d, q);
+input clk, reset, d;
+output q;
+
+reg q;
+wire clk, reset, d;
+
+always @ (posedge clk or posedge reset)
+if (reset) begin
+ q <= 1'b0;
+end else begin
+ q <= d;
+end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_syn_reset.v b/tests/asicworld/code_tidbits_syn_reset.v
new file mode 100644
index 00000000..994771b1
--- /dev/null
+++ b/tests/asicworld/code_tidbits_syn_reset.v
@@ -0,0 +1,19 @@
+module syn_reset (clk,reset,a,c);
+ input clk;
+ input reset;
+ input a;
+ output c;
+
+ wire clk;
+ wire reset;
+ wire a;
+ reg c;
+
+always @ (posedge clk )
+ if ( reset == 1'b1) begin
+ c <= 0;
+ end else begin
+ c <= a;
+ end
+
+endmodule
diff --git a/tests/asicworld/code_tidbits_wire_example.v b/tests/asicworld/code_tidbits_wire_example.v
new file mode 100644
index 00000000..577a535d
--- /dev/null
+++ b/tests/asicworld/code_tidbits_wire_example.v
@@ -0,0 +1,9 @@
+module wire_example( a, b, y);
+ input a, b;
+ output y;
+
+ wire a, b, y;
+
+ assign y = a & b;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_addbit.v b/tests/asicworld/code_verilog_tutorial_addbit.v
new file mode 100644
index 00000000..22063b05
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_addbit.v
@@ -0,0 +1,24 @@
+module addbit (
+a , // first input
+b , // Second input
+ci , // Carry input
+sum , // sum output
+co // carry output
+);
+//Input declaration
+input a;
+input b;
+input ci;
+//Ouput declaration
+output sum;
+output co;
+//Port Data types
+wire a;
+wire b;
+wire ci;
+wire sum;
+wire co;
+//Code starts here
+assign {co,sum} = a + b + ci;
+
+endmodule // End of Module addbit
diff --git a/tests/asicworld/code_verilog_tutorial_always_example.v b/tests/asicworld/code_verilog_tutorial_always_example.v
new file mode 100644
index 00000000..8b0fc206
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_always_example.v
@@ -0,0 +1,11 @@
+module always_example();
+reg clk,reset,enable,q_in,data;
+
+always @ (posedge clk)
+if (reset) begin
+ data <= 0;
+end else if (enable) begin
+ data <= q_in;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_bus_con.v b/tests/asicworld/code_verilog_tutorial_bus_con.v
new file mode 100644
index 00000000..b100c813
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_bus_con.v
@@ -0,0 +1,8 @@
+module bus_con (a,b, y);
+ input [3:0] a, b;
+ output [7:0] y;
+ wire [7:0] y;
+
+ assign y = {a,b};
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_comment.v b/tests/asicworld/code_verilog_tutorial_comment.v
new file mode 100644
index 00000000..1cc0eb42
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_comment.v
@@ -0,0 +1,25 @@
+/* This is a
+ Multi line comment
+ example */
+module addbit (
+a,
+b,
+ci,
+sum,
+co);
+
+// Input Ports Single line comment
+input a;
+input b;
+input ci;
+// Output ports
+output sum;
+output co;
+// Data Types
+wire a;
+wire b;
+wire ci;
+wire sum;
+wire co;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v
new file mode 100644
index 00000000..53451974
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_counter.v
@@ -0,0 +1,19 @@
+//-----------------------------------------------------
+// Design Name : counter
+// File Name : counter.v
+// Function : 4 bit up counter
+// Coder : Deepak
+//-----------------------------------------------------
+module counter (clk, reset, enable, count);
+input clk, reset, enable;
+output [3:0] count;
+reg [3:0] count;
+
+always @ (posedge clk)
+if (reset == 1'b1) begin
+ count <= 0;
+end else if ( enable == 1'b1) begin
+ count <= count + 1;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v
new file mode 100644
index 00000000..10477938
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v
@@ -0,0 +1,113 @@
+///////////////////////////////////////////////////////////////////////////
+// MODULE : counter_tb //
+// TOP MODULE : -- //
+// //
+// PURPOSE : 4-bit up counter test bench //
+// //
+// DESIGNER : Deepak Kumar Tala //
+// //
+// Revision History //
+// //
+// DEVELOPMENT HISTORY : //
+// Rev0.0 : Jan 03, 2003 //
+// Initial Revision //
+// //
+///////////////////////////////////////////////////////////////////////////
+module testbench;
+
+reg clk, reset, enable;
+wire [3:0] count;
+reg dut_error;
+
+counter U0 (
+.clk (clk),
+.reset (reset),
+.enable (enable),
+.count (count)
+);
+
+event reset_enable;
+event terminate_sim;
+
+initial
+begin
+ $display ("###################################################");
+ clk = 0;
+ reset = 0;
+ enable = 0;
+ dut_error = 0;
+end
+
+always
+ #5 clk = !clk;
+
+initial
+begin
+ $dumpfile ("counter.vcd");
+ $dumpvars;
+end
+
+
+initial
+@ (terminate_sim) begin
+ $display ("Terminating simulation");
+ if (dut_error == 0) begin
+ $display ("Simulation Result : PASSED");
+ end
+ else begin
+ $display ("Simulation Result : FAILED");
+ end
+ $display ("###################################################");
+ #1 $finish;
+end
+
+
+
+event reset_done;
+
+initial
+forever begin
+ @ (reset_enable);
+ @ (negedge clk)
+ $display ("Applying reset");
+ reset = 1;
+ @ (negedge clk)
+ reset = 0;
+ $display ("Came out of Reset");
+ -> reset_done;
+end
+
+initial begin
+ #10 -> reset_enable;
+ @ (reset_done);
+ @ (negedge clk);
+ enable = 1;
+ repeat (5)
+ begin
+ @ (negedge clk);
+ end
+ enable = 0;
+ #5 -> terminate_sim;
+end
+
+
+reg [3:0] count_compare;
+
+always @ (posedge clk)
+if (reset == 1'b1)
+ count_compare <= 0;
+else if ( enable == 1'b1)
+ count_compare <= count_compare + 1;
+
+
+
+always @ (negedge clk)
+if (count_compare != count) begin
+ $display ("DUT ERROR AT TIME%d",$time);
+ $display ("Expected value %d, Got Value %d", count_compare, count);
+ dut_error = 1;
+ #5 -> terminate_sim;
+end
+
+endmodule
+
diff --git a/tests/asicworld/code_verilog_tutorial_d_ff.v b/tests/asicworld/code_verilog_tutorial_d_ff.v
new file mode 100644
index 00000000..7a408360
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_d_ff.v
@@ -0,0 +1,14 @@
+// D flip-flop Code
+module d_ff ( d, clk, q, q_bar);
+input d ,clk;
+output q, q_bar;
+wire d ,clk;
+reg q, q_bar;
+
+always @ (posedge clk)
+begin
+ q <= d;
+ q_bar <= !d;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_decoder.v b/tests/asicworld/code_verilog_tutorial_decoder.v
new file mode 100644
index 00000000..5efdbd7e
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_decoder.v
@@ -0,0 +1,14 @@
+module decoder (in,out);
+input [2:0] in;
+output [7:0] out;
+wire [7:0] out;
+assign out = (in == 3'b000 ) ? 8'b0000_0001 :
+(in == 3'b001 ) ? 8'b0000_0010 :
+(in == 3'b010 ) ? 8'b0000_0100 :
+(in == 3'b011 ) ? 8'b0000_1000 :
+(in == 3'b100 ) ? 8'b0001_0000 :
+(in == 3'b101 ) ? 8'b0010_0000 :
+(in == 3'b110 ) ? 8'b0100_0000 :
+(in == 3'b111 ) ? 8'b1000_0000 : 8'h00;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_decoder_always.v b/tests/asicworld/code_verilog_tutorial_decoder_always.v
new file mode 100644
index 00000000..4418ec70
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_decoder_always.v
@@ -0,0 +1,20 @@
+module decoder_always (in,out);
+input [2:0] in;
+output [7:0] out;
+reg [7:0] out;
+
+always @ (in)
+begin
+ out = 0;
+ case (in)
+ 3'b001 : out = 8'b0000_0001;
+ 3'b010 : out = 8'b0000_0010;
+ 3'b011 : out = 8'b0000_0100;
+ 3'b100 : out = 8'b0000_1000;
+ 3'b101 : out = 8'b0001_0000;
+ 3'b110 : out = 8'b0100_0000;
+ 3'b111 : out = 8'b1000_0000;
+ endcase
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_escape_id.v b/tests/asicworld/code_verilog_tutorial_escape_id.v
new file mode 100644
index 00000000..6c33da17
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_escape_id.v
@@ -0,0 +1,14 @@
+// There must be white space after the
+// string which uses escape character
+module \1dff (
+q, // Q output
+\q~ , // Q_out output
+d, // D input
+cl$k, // CLOCK input
+\reset* // Reset input
+);
+
+input d, cl$k, \reset* ;
+output q, \q~ ;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_explicit.v b/tests/asicworld/code_verilog_tutorial_explicit.v
new file mode 100644
index 00000000..88427ff0
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_explicit.v
@@ -0,0 +1,35 @@
+module explicit();
+reg clk,d,rst,pre;
+wire q;
+
+// Here q_bar is not connected
+// We can connect ports in any order
+dff u0 (
+.q (q),
+.d (d),
+.clk (clk),
+.q_bar (),
+.rst (rst),
+.pre (pre)
+);
+
+endmodule
+
+// D fli-flop
+module dff (q, q_bar, clk, d, rst, pre);
+input clk, d, rst, pre;
+output q, q_bar;
+reg q;
+
+assign q_bar = ~q;
+
+always @ (posedge clk)
+if (rst == 1'b1) begin
+ q <= 0;
+end else if (pre == 1'b1) begin
+ q <= 1;
+end else begin
+ q <= d;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_first_counter.v b/tests/asicworld/code_verilog_tutorial_first_counter.v
new file mode 100644
index 00000000..d35d4aac
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_first_counter.v
@@ -0,0 +1,47 @@
+//-----------------------------------------------------
+// This is my second Verilog Design
+// Design Name : first_counter
+// File Name : first_counter.v
+// Function : This is a 4 bit up-counter with
+// Synchronous active high reset and
+// with active high enable signal
+//-----------------------------------------------------
+module first_counter (
+clock , // Clock input of the design
+reset , // active high, synchronous Reset input
+enable , // Active high enable signal for counter
+counter_out // 4 bit vector output of the counter
+); // End of port list
+//-------------Input Ports-----------------------------
+input clock ;
+input reset ;
+input enable ;
+//-------------Output Ports----------------------------
+output [3:0] counter_out ;
+//-------------Input ports Data Type-------------------
+// By rule all the input ports should be wires
+wire clock ;
+wire reset ;
+wire enable ;
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [3:0] counter_out ;
+
+//------------Code Starts Here-------------------------
+// Since this counter is a positive edge trigged one,
+// We trigger the below block with respect to positive
+// edge of the clock.
+always @ (posedge clock)
+begin : COUNTER // Block Name
+ // At every rising edge of clock we check if reset is active
+ // If active, we load the counter output with 4'b0000
+ if (reset == 1'b1) begin
+ counter_out <= 4'b0000;
+ end
+ // If enable is active, then we increment the counter
+ else if (enable == 1'b1) begin
+ counter_out <= counter_out + 1;
+ end
+end // End of Block COUNTER
+
+endmodule // End of Module counter
diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
new file mode 100644
index 00000000..f065732b
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
@@ -0,0 +1,36 @@
+module testbench();
+// Declare inputs as regs and outputs as wires
+reg clock, reset, enable;
+wire [3:0] counter_out;
+
+// Initialize all variables
+initial begin
+ $display ("time\t clk reset enable counter");
+ $monitor ("%g\t %b %b %b %b",
+ $time, clock, reset, enable, counter_out);
+ clock = 1; // initial value of clock
+ reset = 0; // initial value of reset
+ enable = 0; // initial value of enable
+ #5 reset = 1; // Assert the reset
+ #10 reset = 0; // De-assert the reset
+ #10 enable = 1; // Assert enable
+ #100 enable = 0; // De-assert enable
+ #5 $finish; // Terminate simulation
+end
+
+// Clock generator
+initial begin
+ #1;
+ forever
+ #5 clock = ~clock; // Toggle clock every 5 ticks
+end
+
+// Connect DUT to test bench
+first_counter U_counter (
+clock,
+reset,
+enable,
+counter_out
+);
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_flip_flop.v b/tests/asicworld/code_verilog_tutorial_flip_flop.v
new file mode 100644
index 00000000..ed2e88c2
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_flip_flop.v
@@ -0,0 +1,15 @@
+module flif_flop (clk,reset, q, d);
+input clk, reset, d;
+output q;
+reg q;
+
+always @ (posedge clk )
+begin
+ if (reset == 1) begin
+ q <= 0;
+ end else begin
+ q <= d;
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full.v b/tests/asicworld/code_verilog_tutorial_fsm_full.v
new file mode 100644
index 00000000..fd2d559b
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_fsm_full.v
@@ -0,0 +1,114 @@
+module fsm_full(
+clock , // Clock
+reset , // Active high reset
+req_0 , // Active high request from agent 0
+req_1 , // Active high request from agent 1
+req_2 , // Active high request from agent 2
+req_3 , // Active high request from agent 3
+gnt_0 , // Active high grant to agent 0
+gnt_1 , // Active high grant to agent 1
+gnt_2 , // Active high grant to agent 2
+gnt_3 // Active high grant to agent 3
+);
+// Port declaration here
+input clock ; // Clock
+input reset ; // Active high reset
+input req_0 ; // Active high request from agent 0
+input req_1 ; // Active high request from agent 1
+input req_2 ; // Active high request from agent 2
+input req_3 ; // Active high request from agent 3
+output gnt_0 ; // Active high grant to agent 0
+output gnt_1 ; // Active high grant to agent 1
+output gnt_2 ; // Active high grant to agent 2
+output gnt_3 ; // Active high grant to agent
+
+// Internal Variables
+reg gnt_0 ; // Active high grant to agent 0
+reg gnt_1 ; // Active high grant to agent 1
+reg gnt_2 ; // Active high grant to agent 2
+reg gnt_3 ; // Active high grant to agent
+
+parameter [2:0] IDLE = 3'b000;
+parameter [2:0] GNT0 = 3'b001;
+parameter [2:0] GNT1 = 3'b010;
+parameter [2:0] GNT2 = 3'b011;
+parameter [2:0] GNT3 = 3'b100;
+
+reg [2:0] state, next_state;
+
+always @ (state or req_0 or req_1 or req_2 or req_3)
+begin
+ next_state = 0;
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ next_state = GNT0;
+ end else if (req_1 == 1'b1) begin
+ next_state= GNT1;
+ end else if (req_2 == 1'b1) begin
+ next_state= GNT2;
+ end else if (req_3 == 1'b1) begin
+ next_state= GNT3;
+ end else begin
+ next_state = IDLE;
+ end
+ GNT0 : if (req_0 == 1'b0) begin
+ next_state = IDLE;
+ end else begin
+ next_state = GNT0;
+ end
+ GNT1 : if (req_1 == 1'b0) begin
+ next_state = IDLE;
+ end else begin
+ next_state = GNT1;
+ end
+ GNT2 : if (req_2 == 1'b0) begin
+ next_state = IDLE;
+ end else begin
+ next_state = GNT2;
+ end
+ GNT3 : if (req_3 == 1'b0) begin
+ next_state = IDLE;
+ end else begin
+ next_state = GNT3;
+ end
+ default : next_state = IDLE;
+ endcase
+end
+
+always @ (posedge clock)
+begin : OUTPUT_LOGIC
+ if (reset) begin
+ gnt_0 <= 1'b0;
+ gnt_1 <= 1'b0;
+ gnt_2 <= 1'b0;
+ gnt_3 <= 1'b0;
+ state <= IDLE;
+ end else begin
+ state <= next_state;
+ case(state)
+ IDLE : begin
+ gnt_0 <= 1'b0;
+ gnt_1 <= 1'b0;
+ gnt_2 <= 1'b0;
+ gnt_3 <= 1'b0;
+ end
+ GNT0 : begin
+ gnt_0 <= 1'b1;
+ end
+ GNT1 : begin
+ gnt_1 <= 1'b1;
+ end
+ GNT2 : begin
+ gnt_2 <= 1'b1;
+ end
+ GNT3 : begin
+ gnt_3 <= 1'b1;
+ end
+ default : begin
+ state <= IDLE;
+ end
+ endcase
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
new file mode 100644
index 00000000..0097b1c9
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
@@ -0,0 +1,48 @@
+module testbench();
+reg clock , reset ;
+reg req_0 , req_1 , req_2 , req_3;
+wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
+
+initial begin
+ $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3");
+ $monitor("%g\t %b %b %b %b %b %b %b %b",
+ $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
+ clock = 0;
+ reset = 0;
+ req_0 = 0;
+ req_1 = 0;
+ req_2 = 0;
+ req_3 = 0;
+ #10 reset = 1;
+ #10 reset = 0;
+ #10 req_0 = 1;
+ #20 req_0 = 0;
+ #10 req_1 = 1;
+ #20 req_1 = 0;
+ #10 req_2 = 1;
+ #20 req_2 = 0;
+ #10 req_3 = 1;
+ #20 req_3 = 0;
+ #10 $finish;
+end
+
+initial begin
+ #1;
+ forever
+ #2 clock = ~clock;
+end
+
+fsm_full U_fsm_full(
+clock , // Clock
+reset , // Active high reset
+req_0 , // Active high request from agent 0
+req_1 , // Active high request from agent 1
+req_2 , // Active high request from agent 2
+req_3 , // Active high request from agent 3
+gnt_0 , // Active high grant to agent 0
+gnt_1 , // Active high grant to agent 1
+gnt_2 , // Active high grant to agent 2
+gnt_3 // Active high grant to agent 3
+);
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_good_code.v b/tests/asicworld/code_verilog_tutorial_good_code.v
new file mode 100644
index 00000000..6ba77644
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_good_code.v
@@ -0,0 +1,18 @@
+ module addbit (
+ a,
+ b,
+ ci,
+ sum,
+ co);
+ input a;
+ input b;
+ input ci;
+ output sum;
+ output co;
+ wire a;
+ wire b;
+ wire ci;
+ wire sum;
+ wire co;
+
+ endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_if_else.v b/tests/asicworld/code_verilog_tutorial_if_else.v
new file mode 100644
index 00000000..19b91d3f
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_if_else.v
@@ -0,0 +1,13 @@
+module if_else();
+
+reg dff;
+wire clk,din,reset;
+
+always @ (posedge clk)
+if (reset) begin
+ dff <= 0;
+end else begin
+ dff <= din;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_multiply.v b/tests/asicworld/code_verilog_tutorial_multiply.v
new file mode 100644
index 00000000..1912e1e2
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_multiply.v
@@ -0,0 +1,8 @@
+module muliply (a,product);
+ input [3:0] a;
+ output [4:0] product;
+ wire [4:0] product;
+
+ assign product = a << 1;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_mux_21.v b/tests/asicworld/code_verilog_tutorial_mux_21.v
new file mode 100644
index 00000000..a6a0d35e
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_mux_21.v
@@ -0,0 +1,9 @@
+module mux_21 (a,b,sel,y);
+ input a, b;
+ output y;
+ input sel;
+ wire y;
+
+ assign y = (sel) ? b : a;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_n_out_primitive.v b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v
new file mode 100644
index 00000000..814385a4
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v
@@ -0,0 +1,13 @@
+module n_out_primitive();
+
+wire out,out_0,out_1,out_2,out_3,out_a,out_b,out_c;
+wire in;
+
+// one output Buffer gate
+buf u_buf0 (out,in);
+// four output Buffer gate
+buf u_buf1 (out_0, out_1, out_2, out_3, in);
+// three output Invertor gate
+not u_not0 (out_a, out_b, out_c, in);
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_parallel_if.v b/tests/asicworld/code_verilog_tutorial_parallel_if.v
new file mode 100644
index 00000000..1dbe737e
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_parallel_if.v
@@ -0,0 +1,21 @@
+module parallel_if();
+
+reg [3:0] counter;
+wire clk,reset,enable, up_en, down_en;
+
+always @ (posedge clk)
+// If reset is asserted
+if (reset == 1'b0) begin
+ counter <= 4'b0000;
+end else begin
+ // If counter is enable and up count is mode
+ if (enable == 1'b1 && up_en == 1'b1) begin
+ counter <= counter + 1'b1;
+ end
+ // If counter is enable and down count is mode
+ if (enable == 1'b1 && down_en == 1'b1) begin
+ counter <= counter - 1'b1;
+ end
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_parity.v b/tests/asicworld/code_verilog_tutorial_parity.v
new file mode 100644
index 00000000..764396c2
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_parity.v
@@ -0,0 +1,41 @@
+//-----------------------------------------------------
+// This is simple parity Program
+// Design Name : parity
+// File Name : parity.v
+// Function : This program shows how a verilog
+// primitive/module port connection are done
+// Coder : Deepak
+//-----------------------------------------------------
+module parity (
+a , // First input
+b , // Second input
+c , // Third Input
+d , // Fourth Input
+y // Parity output
+);
+
+// Input Declaration
+input a ;
+input b ;
+input c ;
+input d ;
+// Ouput Declaration
+output y ;
+// port data types
+wire a ;
+wire b ;
+wire c ;
+wire d ;
+wire y ;
+// Internal variables
+wire out_0 ;
+wire out_1 ;
+
+// Code starts Here
+xor u0 (out_0,a,b);
+
+xor u1 (out_1,c,d);
+
+xor u2 (y,out_0,out_1);
+
+endmodule // End Of Module parity
diff --git a/tests/asicworld/code_verilog_tutorial_simple_function.v b/tests/asicworld/code_verilog_tutorial_simple_function.v
new file mode 100644
index 00000000..5818a1d4
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_simple_function.v
@@ -0,0 +1,10 @@
+module simple_function();
+
+function myfunction;
+input a, b, c, d;
+begin
+ myfunction = ((a+b) + (c-d));
+end
+endfunction
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_simple_if.v b/tests/asicworld/code_verilog_tutorial_simple_if.v
new file mode 100644
index 00000000..a68cc4a8
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_simple_if.v
@@ -0,0 +1,11 @@
+module simple_if();
+
+reg latch;
+wire enable,din;
+
+always @ (enable or din)
+if (enable) begin
+ latch <= din;
+end
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_task_global.v b/tests/asicworld/code_verilog_tutorial_task_global.v
new file mode 100644
index 00000000..3ae86279
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_task_global.v
@@ -0,0 +1,12 @@
+module task_global();
+
+reg [7:0] temp_out;
+reg [7:0] temp_in;
+
+task convert;
+begin
+ temp_out = (9/5) *( temp_in + 32);
+end
+endtask
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_tri_buf.v b/tests/asicworld/code_verilog_tutorial_tri_buf.v
new file mode 100644
index 00000000..a55b29ca
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_tri_buf.v
@@ -0,0 +1,9 @@
+module tri_buf (a,b,enable);
+ input a;
+ output b;
+ input enable;
+ wire b;
+
+assign b = (enable) ? a : 1'bz;
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_v2k_reg.v b/tests/asicworld/code_verilog_tutorial_v2k_reg.v
new file mode 100644
index 00000000..537a9e85
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_v2k_reg.v
@@ -0,0 +1,24 @@
+module v2k_reg();
+
+// v2k allows to init variables
+reg a = 0;
+// Here only last variable is set to 0, i.e d = 0
+// Rest b, c are set to x
+reg b, c, d = 0;
+// reg data type can be signed in v2k
+// We can assign with signed constants
+reg signed [7:0] data = 8'shF0;
+
+// Function can return signed values
+// Its ports can contain signed ports
+function signed [7:0] adder;
+ input a_in;
+ input b_in;
+ input c_in;
+ input signed [7:0] data_in;
+ begin
+ adder = a_in + b_in + c_in + data_in;
+ end
+endfunction
+
+endmodule
diff --git a/tests/asicworld/code_verilog_tutorial_which_clock.v b/tests/asicworld/code_verilog_tutorial_which_clock.v
new file mode 100644
index 00000000..418a2cfa
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_which_clock.v
@@ -0,0 +1,12 @@
+module which_clock (x,y,q,d);
+input x,y,d;
+output q;
+reg q;
+
+always @ (posedge x or posedge y)
+ if (x)
+ q <= 1'b0;
+ else
+ q <= d;
+
+endmodule
diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh
new file mode 100755
index 00000000..bf27d15f
--- /dev/null
+++ b/tests/asicworld/run-test.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+make -C ../.. || exit 1
+exec bash ../tools/autotest.sh *.v