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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-11-03 23:18:00 +0100 |
| commit | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (patch) | |
| tree | adb13b830212c269d58031f900d652f29013d2d7 /tests/bram/run-single.sh | |
| parent | 4f096fe65b77435daba019248273e547fa18d167 (diff) | |
Imported yosys 0.7
Diffstat (limited to 'tests/bram/run-single.sh')
| -rw-r--r-- | tests/bram/run-single.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 19a235c7..98a45b61 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -2,7 +2,7 @@ set -e ../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v -iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ +iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt if grep -q ERROR temp/tb_${1}_${2}.txt; then |