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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-03 10:57:01 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-03 10:57:01 +0100 |
| commit | a7e43ae3d97ef14c8d624d8fdfe938ae9f47ce84 (patch) | |
| tree | 6d6e97eef96e519e273ee7fc34c53acff29f5061 /tests/bram/run-single.sh | |
| parent | 146f769beef2f6affa9df8e8265e0ca6519d3554 (diff) | |
Progress in memory_bram
Diffstat (limited to 'tests/bram/run-single.sh')
| -rw-r--r-- | tests/bram/run-single.sh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 8a022e59..cb8295d1 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -2,8 +2,8 @@ set -e ../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v -iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \ - temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v +iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ + temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt if grep -q ERROR temp/tb_${1}_${2}.txt; then grep -HC2 ERROR temp/tb_${1}_${2}.txt | head |