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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-03 17:40:20 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-03 17:40:20 +0100 |
| commit | 45918b8315423cb91400a0127550a1d54220c447 (patch) | |
| tree | dde47f7a5f8c3056c93ccb8e7f38d18296b645de /tests/bram | |
| parent | a7fe87f8886900b3e9056caf392978e06c5a74ae (diff) | |
Added "memory -bram"
Diffstat (limited to 'tests/bram')
| -rw-r--r-- | tests/bram/run-single.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index cb8295d1..19a235c7 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,6 +1,6 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap; memory_bram -rules temp/brams_${2}.txt; opt -fast -full" \ +../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v |