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authorClifford Wolf <clifford@clifford.at>2014-08-12 15:43:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-12 15:43:30 +0200
commit1dd8252169654c2bc8cb96a90141a333d3ccd4f6 (patch)
tree548236e33cb579c6471fbfda2ded319e5cbd83b1 /tests/fsm/generate.py
parente5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4 (diff)
Added test_verific mode to tests/fsm/generate.py
Diffstat (limited to 'tests/fsm/generate.py')
-rw-r--r--tests/fsm/generate.py24
1 files changed, 17 insertions, 7 deletions
diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py
index ca0718b2..66ca2af5 100644
--- a/tests/fsm/generate.py
+++ b/tests/fsm/generate.py
@@ -7,6 +7,9 @@ import sys
import random
from contextlib import contextmanager
+# set to 'True' to compare verific with yosys
+test_verific = False
+
@contextmanager
def redirect_stdout(new_target):
old_target, sys.stdout = sys.stdout, new_target
@@ -86,13 +89,20 @@ for idx in range(50):
print(' end')
print('endmodule')
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
- print('read_verilog temp/uut_%05d.v' % idx)
- print('proc;;')
- print('copy uut_%05d gold' % idx)
- print('rename uut_%05d gate' % idx)
- print('cd gate')
- print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
- print('cd ..')
+ if test_verific:
+ print('read_verilog temp/uut_%05d.v' % idx)
+ print('proc;; rename uut_%05d gold' % idx)
+ print('verific -vlog2k temp/uut_%05d.v' % idx)
+ print('verific -import uut_%05d' % idx)
+ print('rename uut_%05d gate' % idx)
+ else:
+ print('read_verilog temp/uut_%05d.v' % idx)
+ print('proc;;')
+ print('copy uut_%05d gold' % idx)
+ print('rename uut_%05d gate' % idx)
+ print('cd gate')
+ print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive']))
+ print('cd ..')
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))