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authorClifford Wolf <clifford@clifford.at>2015-05-11 21:46:35 +0200
committerClifford Wolf <clifford@clifford.at>2015-05-11 21:58:21 +0200
commitdae00e1d8301aae25f3432ca12995c9a3b380679 (patch)
treeb55a32f53afa4611a6c3a1ef824b2b22b95dcc2e /tests/fsm/generate.py
parent42348cddd9218f198e93bc11909e7b118a71c9ba (diff)
changed file() to open() in python scripts
Diffstat (limited to 'tests/fsm/generate.py')
-rw-r--r--tests/fsm/generate.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py
index fc67543f..352eedb0 100644
--- a/tests/fsm/generate.py
+++ b/tests/fsm/generate.py
@@ -34,7 +34,7 @@ def random_expr(variables):
raise AssertionError
for idx in range(50):
- with file('temp/uut_%05d.v' % idx, 'w') as f:
+ with open('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
rst2 = random.choice([False, True])
if rst2:
@@ -90,7 +90,7 @@ for idx in range(50):
print(' end')
print(' end')
print('endmodule')
- with file('temp/uut_%05d.ys' % idx, 'w') as f:
+ with open('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
if test_verific:
print('read_verilog temp/uut_%05d.v' % idx)