initial import

3 files changed, 72 insertions, 0 deletions

diff --git a/tests/no-icarus/README b/tests/no-icarus/README
new file mode 100644
index 00000000..b43e7c02
--- /dev/null
+++ b/tests/no-icarus/README
@@ -0,0 +1,2 @@
+This directory contains test cases that can't be tested using Icarus Verilog
+because they exceed the Verilog subset that is supported by Icarus Verilog.
diff --git a/tests/no-icarus/autowire.v b/tests/no-icarus/autowire.v
new file mode 100644
index 00000000..3633d427
--- /dev/null
+++ b/tests/no-icarus/autowire.v
@@ -0,0 +1,25 @@
+
+module test01(a, b, y);
+
+input [3:0] a, b;
+output [3:0] y;
+
+assign temp1 = a + b;
+assign temp2 = ~temp1;
+assign y = temp2;
+
+endmodule
+
+// ------------------------------
+
+module test02(a, b, y);
+
+input [3:0] a, b;
+output [3:0] y;
+
+test01 test01_cell(A, B, Y);
+
+assign A = a, B = b, y = Y;
+
+endmodule
+
diff --git a/tests/no-icarus/var_range.v b/tests/no-icarus/var_range.v
new file mode 100644
index 00000000..431eacb8
--- /dev/null
+++ b/tests/no-icarus/var_range.v
@@ -0,0 +1,45 @@
+
+module test01(a, b, x, y, z);
+
+input [7:0] a;
+input [2:0] b;
+output [7:0] x, y;
+output z;
+
+assign x = a >> b;
+assign y = a[b+7:b];
+assign z = a[b];
+
+endmodule
+
+module test02(clk, a, b, x, y, z);
+
+input clk;
+input [7:0] a;
+input [2:0] b;
+output reg [7:0] x, y;
+output reg z;
+
+always @(posedge clk) begin
+	x <= a >> b;
+	y <= a[b+7:b];
+	z <= a[b];
+end
+
+endmodule
+
+module test03(clk, a, b, x, y);
+
+input clk;
+input [2:0] a, b;
+output reg [7:0] x;
+output reg [9:0] y;
+
+always @(posedge clk)
+	y[b] <= a;
+
+always @(posedge clk)
+	y[b+2:b] <= a;
+
+endmodule
+