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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/openmsp430/sim_mul.v |
initial import
Diffstat (limited to 'tests/openmsp430/sim_mul.v')
-rw-r--r-- | tests/openmsp430/sim_mul.v | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/openmsp430/sim_mul.v b/tests/openmsp430/sim_mul.v new file mode 100644 index 00000000..8762bb25 --- /dev/null +++ b/tests/openmsp430/sim_mul.v @@ -0,0 +1,29 @@ + +module \$mul (A, B, Y); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; + +input [A_WIDTH-1:0] A; +generate if (A_SIGNED) begin:A_BUF + wire signed [A_WIDTH-1:0] val = A; +end else begin:A_BUF + wire [A_WIDTH-1:0] val = A; +end endgenerate + +input [B_WIDTH-1:0] B; +generate if (B_SIGNED) begin:B_BUF + wire signed [B_WIDTH-1:0] val = B; +end else begin:B_BUF + wire [B_WIDTH-1:0] val = B; +end endgenerate + +output [Y_WIDTH-1:0] Y; + +assign Y = A_BUF.val * B_BUF.val; + +endmodule + |