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authorClifford Wolf <clifford@clifford.at>2013-01-05 11:13:26 +0100
committerClifford Wolf <clifford@clifford.at>2013-01-05 11:13:26 +0100
commit7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch)
tree18c05b8729df381af71b707748ce1d605e0df764 /tests/or1200/run-synth.sh
initial import
Diffstat (limited to 'tests/or1200/run-synth.sh')
-rw-r--r--tests/or1200/run-synth.sh2
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/or1200/run-synth.sh b/tests/or1200/run-synth.sh
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+#!/bin/bash
+time ../../yosys -b "verilog -noexpr" -o synth.v -tl synth.log -s run-synth.ys rtl/or1200_*.v 2>&1 | egrep '^\[[0-9.]+\] (ERROR|--|[0-9]+\.)'