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authorClifford Wolf <clifford@clifford.at>2014-07-05 11:17:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-05 11:18:38 +0200
commit3b52121d328d45a5d4269fd0e8de9af948c0216e (patch)
tree59d61572353b98e449d72f4802c4e7c164f7b5eb /tests/sat
parentee8ad72fd950e1ee204e5c97155a50b8b1445dec (diff)
now ignore init attributes on non-register wires in sat command
Diffstat (limited to 'tests/sat')
-rw-r--r--tests/sat/initval.v15
-rw-r--r--tests/sat/initval.ys4
2 files changed, 19 insertions, 0 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v
new file mode 100644
index 00000000..5b661f8d
--- /dev/null
+++ b/tests/sat/initval.v
@@ -0,0 +1,15 @@
+module test(input clk, input [3:0] bar, output [3:0] foo);
+ reg [3:0] foo = 0;
+ reg [3:0] last_bar = 0;
+
+ always @*
+ foo[1:0] <= bar[1:0];
+
+ always @(posedge clk)
+ foo[3:2] <= bar[3:2];
+
+ always @(posedge clk)
+ last_bar <= bar;
+
+ assert property (foo == {last_bar[3:2], bar[1:0]});
+endmodule
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
new file mode 100644
index 00000000..2079d2f3
--- /dev/null
+++ b/tests/sat/initval.ys
@@ -0,0 +1,4 @@
+read_verilog -sv initval.v
+proc;;
+
+sat -seq 10 -prove-asserts