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author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:55 +0000 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:55 +0000 |
commit | b9e09c69c0570486f3f8a73499049b636a4b4c34 (patch) | |
tree | e36d38108251cdbc8ed83721a9ae06da73cfd848 /tests/simple/arrays02.sv | |
parent | 3c2327501d79de3f007014c1fd8817c95c477aa4 (diff) | |
parent | 1f6bb85359149a016811e7e7fef980c3d45211e7 (diff) |
Update upstream source from tag 'upstream/0.9'
Update to upstream version '0.9'
with Debian dir df447efe4e1efaece1d926cd037de4a7c3c1bebe
Diffstat (limited to 'tests/simple/arrays02.sv')
-rw-r--r-- | tests/simple/arrays02.sv | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv new file mode 100644 index 00000000..76c2a738 --- /dev/null +++ b/tests/simple/arrays02.sv @@ -0,0 +1,16 @@ +module uut_arrays02(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [16]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule |