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authorRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
committerRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
commit1f6bb85359149a016811e7e7fef980c3d45211e7 (patch)
tree749672f9a104cbfb25bb02acad6cb731724b9d56 /tests/simple/dff_init.v
parentff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff)
New upstream version 0.9
Diffstat (limited to 'tests/simple/dff_init.v')
-rw-r--r--tests/simple/dff_init.v12
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index be947042..375ea5c4 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -40,3 +40,15 @@ module dff1a_test(n1, n1_inv, clk);
n1 <= n1_inv;
assign n1_inv = ~n1;
endmodule
+
+module dff_test_997 (y, clk, wire4);
+// https://github.com/YosysHQ/yosys/issues/997
+ output wire [1:0] y;
+ input clk;
+ input signed wire4;
+ reg [1:0] reg10 = 0;
+ always @(posedge clk) begin
+ reg10 <= wire4;
+ end
+ assign y = reg10;
+endmodule