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authorClifford Wolf <clifford@clifford.at>2013-11-20 13:57:40 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-20 13:57:40 +0100
commit65ad556f3df2f9dc967eda110579e6c355f06102 (patch)
treeaf75d2c0abfe3b199f0f15446f320058bbc23ae9 /tests/simple/rotate.v
parent92035fb38ef8e7ac6319af659f7d682a047d2f70 (diff)
Another name resolution bugfix for generate blocks
Diffstat (limited to 'tests/simple/rotate.v')
-rw-r--r--tests/simple/rotate.v48
1 files changed, 48 insertions, 0 deletions
diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v
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+
+// test case taken from amber23 verilog code
+module a23_barrel_shift_fpga_rotate(i_in, direction, shift_amount, rot_prod);
+
+input [31:0] i_in;
+input direction;
+input [4:0] shift_amount;
+output [31:0] rot_prod;
+
+// Generic rotate. Theoretical cost: 32x5 4-to-1 LUTs.
+// Practically a bit higher due to high fanout of "direction".
+generate
+genvar i, j;
+ for (i = 0; i < 5; i = i + 1)
+ begin : netgen
+ wire [31:0] in;
+ reg [31:0] out;
+ for (j = 0; j < 32; j = j + 1)
+ begin : net
+ always @*
+ out[j] = in[j] & (~shift_amount[i] ^ direction) |
+ in[wrap(j, i)] & (shift_amount[i] ^ direction);
+ end
+ end
+
+ // Order is reverted with respect to volatile shift_amount[0]
+ assign netgen[4].in = i_in;
+ for (i = 1; i < 5; i = i + 1)
+ begin : router
+ assign netgen[i-1].in = netgen[i].out;
+ end
+endgenerate
+
+// Aliasing
+assign rot_prod = netgen[0].out;
+
+function [4:0] wrap;
+input integer pos;
+input integer level;
+integer out;
+begin
+ out = pos - (1 << level);
+ wrap = out[4:0];
+end
+endfunction
+
+endmodule
+