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authorClifford Wolf <clifford@clifford.at>2013-07-09 23:41:28 +0200
committerClifford Wolf <clifford@clifford.at>2013-07-09 23:41:43 +0200
commit5dab327b30cb1d864297b22a15f0fce4b374a841 (patch)
tree6d4bcc104fab5ecd4dd51bae0459ea0144063c27 /tests/simple
parent618b2ac994360de4ffc9299aecb104a5bf5ba721 (diff)
More fixes in ast expression sign/width handling
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/vloghammer.v28
1 files changed, 15 insertions, 13 deletions
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index 9269ff05..09987e7c 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -27,19 +27,21 @@ module test04(a, y);
assign y = ~(a - 1'b0);
endmodule
-module test05(a, y);
- input a;
- output y;
- assign y = 12345 >> {a, 32'd0};
-endmodule
-
-module test06(a, b, c, y);
- input signed [3:0] a;
- input signed [1:0] b;
- input signed [1:0] c;
- output [5:0] y;
- assign y = (a >> b) >>> c;
-endmodule
+// .. this test triggers a bug in xilinx isim.
+// module test05(a, y);
+// input a;
+// output y;
+// assign y = 12345 >> {a, 32'd0};
+// endmodule
+
+// .. this test triggers a bug in icarus verilog.
+// module test06(a, b, c, y);
+// input signed [3:0] a;
+// input signed [1:0] b;
+// input signed [1:0] c;
+// output [5:0] y;
+// assign y = (a >> b) >>> c;
+// endmodule
module test07(a, b, y);
input signed [1:0] a;