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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:17:21 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:17:21 +0100
commit609caa23b5e12547c043dc4a1827d1a531af1992 (patch)
tree297e7d5b77b28eebccc3bd8e7af318f174165744 /tests/simple
parent1e6836933d8b74d391f816ccdcf71c972f8b1db1 (diff)
Implemented correct handling of signed module parameters
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/hierarchy.v8
1 files changed, 7 insertions, 1 deletions
diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 97612c74..17888009 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -4,14 +4,20 @@ module top(a, b, y1, y2, y3, y4);
input [3:0] a;
input signed [3:0] b;
output [7:0] y1, y2, y3, y4;
+
+// this version triggers a bug in icarus verilog
+// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
+
+// this version is handled correctly by icarus verilog
submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
+
endmodule
(* gentb_skip *)
module submod(a, b, y1, y2, y3, y4);
parameter c = 0;
parameter [7:0] d = 0;
-input [7:0] a, b;
+input [3:0] a, b;
output [7:0] y1, y2, y3, y4;
assign y1 = a;
assign y2 = b;