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authorClifford Wolf <clifford@clifford.at>2013-10-24 16:54:05 +0200
committerClifford Wolf <clifford@clifford.at>2013-10-24 16:54:05 +0200
commit628b994cf6223a03d0d57bad193675dc93e88d65 (patch)
tree56dad20ed7d83a6957aa738b59d957b1b89b814f /tests/simple
parente679a5d04633e0c0626057ed2760ddb9595eea5d (diff)
Added support for complex set-reset flip-flops in proc_dff
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/dff_different_styles.v38
1 files changed, 26 insertions, 12 deletions
diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v
index db88b835..2f2737c4 100644
--- a/tests/simple/dff_different_styles.v
+++ b/tests/simple/dff_different_styles.v
@@ -65,6 +65,10 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
end
endmodule
+// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of
+// simulation-implementation mismatches. The following testcases try to cover the
+// part that is defined and avoid the undefined cases.
+
module dffsr1(clk, arst, d, q);
input clk, arst, d;
output reg q;
@@ -76,16 +80,26 @@ always @(posedge clk, posedge arst) begin
end
endmodule
-// module dffsr2(clk, preset, clear, d, q);
-// input clk, preset, clear, d;
-// output reg q;
-// always @(posedge clk, posedge preset, posedge clear) begin
-// if (preset)
-// q <= 1;
-// else if (clear)
-// q <= 0;
-// else
-// q <= d;
-// end
-// endmodule
+module dffsr2(clk, preset, clear, d, q);
+input clk, preset, clear, d;
+output q;
+(* gentb_clock *)
+wire clk, preset, clear, d;
+dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
+endmodule
+
+(* gentb_skip *)
+module dffsr2_sub(clk, preset, clear, d, q);
+input clk, preset, clear, d;
+output reg q;
+always @(posedge clk, posedge preset, posedge clear) begin
+ if (preset)
+ q <= 1;
+ else if (clear)
+ q <= 0;
+ else
+ q <= d;
+end
+endmodule
+