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authorClifford Wolf <clifford@clifford.at>2014-07-17 13:13:21 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-17 13:13:21 +0200
commit6d69d4aaa81f176ec97654b5103f6f59eb98c211 (patch)
tree3c727eeb1afbf57018433ded3494726d0427e1fe /tests/simple
parent1b00861d0a3bba0b609eecde504d8a4f2f9d973d (diff)
Added support for constant bit- or part-select for memory writes
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/memory.v20
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index 927ee043..aae3feac 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -114,3 +114,23 @@ assign rd_data = memory[rd_addr_buf];
endmodule
+// ----------------------------------------------------------
+
+module test05(clk, addr, wdata, rdata, wen);
+
+input clk;
+input [1:0] addr;
+input [7:0] wdata;
+output reg [7:0] rdata;
+input [3:0] wen;
+
+reg [7:0] mem [0:3];
+
+integer i;
+always @(posedge clk) begin
+ for (i = 0; i < 4; i = i+1)
+ if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
+ rdata <= mem[addr];
+end
+
+endmodule