initial import

19 files changed, 905 insertions, 0 deletions

diff --git a/tests/simple/aes_kexp128.v b/tests/simple/aes_kexp128.v
new file mode 100644
index 00000000..3ee03478
--- /dev/null
+++ b/tests/simple/aes_kexp128.v
@@ -0,0 +1,24 @@
+
+// test taken from aes_core from iwls2005
+
+module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
+
+input		clk, kld;
+input	[15:0]	key;
+output	[3:0]	wo_0, wo_1, wo_2, wo_3;
+reg	[3:0]	w[3:0];
+
+assign wo_0 = w[0];
+assign wo_1 = w[1];
+assign wo_2 = w[2];
+assign wo_3 = w[3];
+
+always @(posedge clk) begin
+	w[0] <= kld ? key[15:12] : w[0];
+	w[1] <= kld ? key[11: 8] : w[0]^w[1];
+	w[2] <= kld ? key[ 7: 4] : w[0]^w[1]^w[2];
+	w[3] <= kld ? key[ 3: 0] : w[0]^w[1]^w[2]^w[3];
+end
+
+endmodule
+
diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v
new file mode 100644
index 00000000..23d89b5d
--- /dev/null
+++ b/tests/simple/dff_different_styles.v
@@ -0,0 +1,52 @@
+
+module dff(clk, d, q);
+input clk, d;
+output reg q;
+always @(posedge clk)
+	q <= d;
+endmodule
+
+module dffa(clk, arst, d, q);
+input clk, arst, d;
+output reg q;
+always @(posedge clk or posedge arst) begin
+	if (arst)
+		q <= 1;
+	else
+		q <= d;
+end
+endmodule
+
+module dffa1(clk, arst, d, q);
+input clk, arst, d;
+output reg q;
+always @(posedge clk or negedge arst) begin
+	if (~arst)
+		q <= 0;
+	else
+		q <= d;
+end
+endmodule
+
+module dffa2(clk, arst, d, q);
+input clk, arst, d;
+output reg q;
+always @(posedge clk or negedge arst) begin
+	if (!arst)
+		q <= 0;
+	else
+		q <= d;
+end
+endmodule
+
+module dffa3(clk, arst, d, q);
+input clk, arst, d;
+output reg q;
+always @(posedge clk or negedge arst) begin
+	if (~(!arst))
+		q <= d;
+	else
+		q <= 1;
+end
+endmodule
+
diff --git a/tests/simple/fiedler-cooley.v b/tests/simple/fiedler-cooley.v
new file mode 100644
index 00000000..96861973
--- /dev/null
+++ b/tests/simple/fiedler-cooley.v
@@ -0,0 +1,33 @@
+// borrowed with some modifications from
+// http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
+module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);
+
+input [8:0] data_in;
+input clock, up, down;
+
+output reg [8:0] count_out;
+output reg carry_out, borrow_out, parity_out;
+
+reg [9:0] cnt_up, cnt_dn;
+reg [8:0] count_nxt;
+
+always @(posedge clock)
+begin
+	cnt_dn = count_out - 3'b 101;
+	cnt_up = count_out + 2'b 11;
+
+	case ({up,down})
+		2'b 00 : count_nxt = data_in;
+		2'b 01 : count_nxt = cnt_dn;
+		2'b 10 : count_nxt = cnt_up;
+		2'b 11 : count_nxt = count_out;
+		default : count_nxt = 9'bX;
+	endcase
+
+	parity_out  <= ^count_nxt;
+	carry_out   <= up & cnt_up[9];
+	borrow_out  <= down & cnt_dn[9];
+	count_out   <= count_nxt;
+end
+
+endmodule
diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v
new file mode 100644
index 00000000..79ca041d
--- /dev/null
+++ b/tests/simple/fsm.v
@@ -0,0 +1,69 @@
+
+// `define ASYNC_RESET
+
+module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
+
+input clk, reset, button_a, button_b;
+output reg red_a, green_a, red_b, green_b;
+
+(* gentb_constant = 0 *)
+wire reset;
+
+integer state;
+reg [3:0] cnt;
+
+`ifdef ASYNC_RESET
+always @(posedge clk, posedge reset)
+`else
+always @(posedge clk)
+`endif
+begin
+	cnt <= 0;
+	red_a <= 1;
+	red_b <= 1;
+	green_a <= 0;
+	green_b <= 0;
+
+	if (reset)
+		state <= 100;
+	else
+		case (state)
+			100: begin
+				if (button_a && !button_b)
+					state <= 200;
+				if (!button_a && button_b)
+					state <= 300;
+			end
+			200: begin
+				red_a <= 0;
+				green_a <= 1;
+				cnt <= cnt + 1;
+				if (cnt == 5)
+					state <= 210;
+			end
+			210: begin
+				red_a <= 0;
+				green_a <= cnt[0];
+				cnt <= cnt + 1;
+				if (cnt == 10)
+					state <= 100;
+			end
+			300: begin
+				red_b <= 0;
+				green_b <= 1;
+				cnt <= cnt + 1;
+				if (cnt == 5)
+					state <= 310;
+			end
+			310: begin
+				red_b <= 0;
+				green_b <= cnt[0];
+				cnt <= cnt + 1;
+				if (cnt == 10)
+					state <= 100;
+			end
+		endcase
+end
+
+endmodule
+
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
new file mode 100644
index 00000000..d458c076
--- /dev/null
+++ b/tests/simple/generate.v
@@ -0,0 +1,67 @@
+
+module test1(clk, a, b, y);
+
+input clk;
+input [7:0] a, b;
+output reg [7:0] y;
+
+genvar i, j;
+wire [15:0] tmp1;
+
+generate
+
+	for (i = 0; i < 8; i = i + 1) begin:gen1
+		wire and_wire, or_wire;
+		assign and_wire = a[i] & b[i];
+		assign or_wire = a[i] | b[i];
+		if (i % 2 == 0) begin:gen2true
+			assign tmp1[i] = and_wire;
+			assign tmp1[i+8] = or_wire;
+		end else begin:gen2false
+			assign tmp1[i] = or_wire;
+			assign tmp1[i+8] = and_wire;
+		end
+	end
+
+	for (i = 0; i < 8; i = i + 1) begin:gen3
+		wire [4:0] tmp2;
+		for (j = 0; j <= 4; j = j + 1) begin:gen4
+			wire tmpbuf;
+			assign tmpbuf = tmp1[i+2*j];
+			assign tmp2[j] = tmpbuf;
+		end
+		always @(posedge clk)
+			y[i] <= ^tmp2;
+	end
+
+endgenerate
+
+endmodule
+
+// ------------------------------------------
+
+module test2(clk, a, b, y);
+
+input clk;
+input [7:0] a, b;
+output reg [8:0] y;
+
+integer i;
+reg [8:0] carry;
+
+always @(posedge clk) begin
+	carry[0] = 0;
+	for (i = 0; i < 8; i = i + 1) begin
+		casez ({a[i], b[i], carry[i]})
+			3'b?11, 3'b1?1, 3'b11?:
+				carry[i+1] = 1;
+			default:
+				carry[i+1] = 0;
+		endcase
+		y[i] = a[i] ^ b[i] ^ carry[i];
+	end
+	y[8] = carry[8];
+end
+
+endmodule
+
diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v
new file mode 100644
index 00000000..f8f56408
--- /dev/null
+++ b/tests/simple/i2c_master_tests.v
@@ -0,0 +1,62 @@
+// one of my early test cases was the OpenCores I2C master
+// This is a collection of stripped down code snippets from
+// this core that triggered bugs in early versions of yosys.
+
+// from i2c_master_bit_ctrl
+module test01(clk, rst, nReset, al);
+
+	input clk, rst, nReset;
+	output reg al;
+
+	reg cmd_stop;
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    cmd_stop <= #1 1'b0;
+	  else if (rst)
+	    cmd_stop <= #1 1'b0;
+
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    al <= #1 1'b0;
+	  else if (rst)
+	    al <= #1 1'b0;
+	  else
+	    al <= #1 ~cmd_stop;
+
+endmodule
+
+// from i2c_master_bit_ctrl
+module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
+
+	input clk, slave_wait, clk_cnt;
+	input cmd;
+
+	output reg cmd_stop;
+
+	reg clk_en;
+	output reg [15:0] cnt;
+
+	always @(posedge clk)
+	  if (~|cnt)
+	    if (~slave_wait)
+	      begin
+	          cnt    <= #1 clk_cnt;
+	          clk_en <= #1 1'b1;
+	      end
+	    else
+	      begin
+	          cnt    <= #1 cnt;
+	          clk_en <= #1 1'b0;
+	      end
+	  else
+	    begin
+                cnt    <= #1 cnt - 16'h1;
+	        clk_en <= #1 1'b0;
+	    end
+
+	always @(posedge clk)
+	  if (clk_en)
+	    cmd_stop <= #1 cmd;
+
+endmodule
+
diff --git a/tests/simple/loops.v b/tests/simple/loops.v
new file mode 100644
index 00000000..77cdcd8e
--- /dev/null
+++ b/tests/simple/loops.v
@@ -0,0 +1,79 @@
+
+// a simple test case extracted from systemcaes (as included in iwls2005)
+// this design has latches (or logic loops) for the two temp variables.
+// this latches (or logic loops) must be removed in the final synthesis results
+
+module aes(
+	// inputs
+	input [3:0] addroundkey_data_i,
+	input [3:0] addroundkey_data_reg,
+	input [3:0] addroundkey_round,
+	input [3:0] key_i,
+	input [3:0] keysched_new_key_o,
+	input [3:0] round,
+	input addroundkey_start_i,
+	input keysched_ready_o,
+
+	// outputs
+	output reg [3:0] keysched_last_key_i,
+	output reg [3:0] keysched_round_i,
+	output reg [3:0] next_addroundkey_data_reg,
+	output reg [3:0] next_addroundkey_round,
+	output reg [3:0] round_data_var,
+	output reg keysched_start_i,
+	output reg next_addroundkey_ready_o
+);
+
+// temp variables
+reg [3:0] data_var;
+reg [3:0] round_key_var;
+
+always @*
+begin
+	keysched_start_i = 0;
+	keysched_round_i = addroundkey_round;
+	round_data_var = addroundkey_data_reg;
+	next_addroundkey_data_reg = addroundkey_data_reg;
+	next_addroundkey_ready_o = 0;
+	next_addroundkey_round = addroundkey_round;
+
+	if (addroundkey_round == 1 || addroundkey_round == 0)
+		keysched_last_key_i = key_i;
+	else
+		keysched_last_key_i = keysched_new_key_o;
+	
+	if (round == 0 && addroundkey_start_i)
+	begin
+		data_var = addroundkey_data_i;	
+		round_key_var = key_i;
+		round_data_var = round_key_var ^ data_var;
+		next_addroundkey_data_reg = round_data_var;
+		next_addroundkey_ready_o = 1;
+	end
+	else if (addroundkey_start_i && round != 0)
+	begin
+		keysched_last_key_i = key_i;
+		keysched_start_i = 1;
+		keysched_round_i = 1;
+		next_addroundkey_round = 1;
+	end
+	else if (addroundkey_round != round && keysched_ready_o)
+	begin
+		next_addroundkey_round = addroundkey_round + 1;
+		keysched_last_key_i = keysched_new_key_o;
+		keysched_start_i = 1;
+		keysched_round_i = addroundkey_round + 1;
+	end
+	else if (addroundkey_round == round && keysched_ready_o)
+	begin
+		data_var = addroundkey_data_i;	
+		round_key_var = keysched_new_key_o;
+		round_data_var = round_key_var ^ data_var;
+		next_addroundkey_data_reg = round_data_var;
+		next_addroundkey_ready_o = 1;
+		next_addroundkey_round = 0;
+	end
+end
+
+endmodule
+
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
new file mode 100644
index 00000000..7be32b0b
--- /dev/null
+++ b/tests/simple/mem2reg.v
@@ -0,0 +1,17 @@
+module test1(in_addr, in_data, out_addr, out_data);
+
+input [1:0] in_addr, out_addr;
+input [3:0] in_data;
+output reg [3:0] out_data;
+
+reg [3:0] array [2:0];
+
+always @* begin
+	array[0] = 0;
+	array[1] = 23;
+	array[2] = 42;
+	array[in_addr] = in_data;
+	out_data = array[out_addr];
+end
+
+endmodule
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
new file mode 100644
index 00000000..c25bcd92
--- /dev/null
+++ b/tests/simple/memory.v
@@ -0,0 +1,19 @@
+
+module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
+
+input clk, wr_en;
+input [3:0] wr_addr, rd_addr;
+input [7:0] wr_value;
+output reg [7:0] rd_value;
+
+reg [7:0] data [15:0];
+
+always @(posedge clk)
+	if (wr_en)
+		data[wr_addr] <= wr_value;
+
+always @(posedge clk)
+	rd_value <= data[rd_addr];
+
+endmodule
+
diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v
new file mode 100644
index 00000000..6996206c
--- /dev/null
+++ b/tests/simple/muxtree.v
@@ -0,0 +1,50 @@
+
+// test case generated from IWLS 2005 usb_phy core
+// (triggered a bug in opt_muxtree pass)
+
+module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg);
+
+input		clk;
+input		rst;
+input		DataOut_i;
+input		TxValid_i;
+output reg	hold_reg;
+
+reg		state, next_state;
+reg		ld_sop_d;
+reg		ld_data_d;
+
+always @(posedge clk)
+	if(ld_sop_d)
+		hold_reg <= 0;
+	else
+		hold_reg <= DataOut_i;
+
+always @(posedge clk)
+	if(!rst)	state <= 0;
+	else		state <= next_state;
+
+always @(state or TxValid_i)
+   begin
+	next_state = state;
+
+	ld_sop_d = 1'b0;
+	ld_data_d = 1'b0;
+
+	case(state)	// synopsys full_case parallel_case
+	   0:
+			if(TxValid_i)
+			   begin
+				ld_sop_d = 1'b1;
+				next_state = 1;
+			   end
+	   1:
+			if(TxValid_i)
+			   begin
+				ld_data_d = 1'b1;
+				next_state = 0;
+			   end
+	endcase
+   end
+
+endmodule
diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v
new file mode 100644
index 00000000..dc8860de
--- /dev/null
+++ b/tests/simple/omsp_dbg_uart.v
@@ -0,0 +1,34 @@
+
+module  omsp_dbg_uart (dbg_clk, dbg_rst, mem_burst, cmd_valid);
+
+input dbg_clk;
+input dbg_rst;
+input mem_burst;
+output cmd_valid;
+
+reg [2:0] uart_state;
+reg [2:0] uart_state_nxt;
+
+wire xfer_done;
+
+parameter  RX_SYNC  = 3'h0;
+parameter  RX_CMD   = 3'h1;
+parameter  RX_DATA = 3'h2;
+
+always @(uart_state or mem_burst)
+  case (uart_state)
+    RX_SYNC  : uart_state_nxt =  RX_CMD;
+    RX_CMD   : uart_state_nxt =  mem_burst ? RX_DATA : RX_SYNC;
+    RX_DATA : uart_state_nxt =  RX_SYNC;
+    default  : uart_state_nxt =  RX_CMD;
+  endcase
+   
+always @(posedge dbg_clk or posedge dbg_rst)
+  if (dbg_rst) uart_state <= RX_SYNC;
+  else if (xfer_done | mem_burst) uart_state <= uart_state_nxt;
+
+assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
+assign xfer_done = uart_state!=RX_SYNC;
+   
+endmodule
+
diff --git a/tests/simple/operators.v b/tests/simple/operators.v
new file mode 100644
index 00000000..b9bbc13c
--- /dev/null
+++ b/tests/simple/operators.v
@@ -0,0 +1,97 @@
+
+module test(clk, mode, u1, s1, u2, s2, y);
+
+input clk;
+input [5:0] mode;
+
+input [3:0] u1, u2;
+input signed [3:0] s1, s2;
+
+output reg [7:0] y;
+
+always @(posedge clk) begin
+	y <= 8'h42;
+	case (mode)
+		 0: y <= u1 << u2;
+		 1: y <= u1 << s2;
+		 2: y <= s1 << u2;
+		 3: y <= s1 << s2;
+
+		 4: y <= u1 >> u2;
+		 5: y <= u1 >> s2;
+		 6: y <= s1 >> u2;
+		 7: y <= s1 >> s2;
+
+		 8: y <= u1 <<< u2;
+		 9: y <= u1 <<< s2;
+		10: y <= s1 <<< u2;
+		11: y <= s1 <<< s2;
+
+		12: y <= u1 >>> u2;
+		13: y <= u1 >>> s2;
+		14: y <= s1 >>> u2;
+		15: y <= s1 >>> s2;
+
+		16: y <= u1 < u2;
+		17: y <= u1 < s2;
+		18: y <= s1 < u2;
+		19: y <= s1 < s2;
+
+		20: y <= u1 <= u2;
+		21: y <= u1 <= s2;
+		22: y <= s1 <= u2;
+		23: y <= s1 <= s2;
+
+		24: y <= u1 == u2;
+		25: y <= u1 == s2;
+		26: y <= s1 == u2;
+		27: y <= s1 == s2;
+
+		28: y <= u1 != u2;
+		29: y <= u1 != s2;
+		30: y <= s1 != u2;
+		31: y <= s1 != s2;
+
+		32: y <= u1 >= u2;
+		33: y <= u1 >= s2;
+		34: y <= s1 >= u2;
+		35: y <= s1 >= s2;
+
+		36: y <= u1 > u2;
+		37: y <= u1 > s2;
+		38: y <= s1 > u2;
+		39: y <= s1 > s2;
+
+		40: y <= u1 + u2;
+		41: y <= u1 + s2;
+		42: y <= s1 + u2;
+		43: y <= s1 + s2;
+
+		44: y <= u1 - u2;
+		45: y <= u1 - s2;
+		46: y <= s1 - u2;
+		47: y <= s1 - s2;
+
+		48: y <= +u1;
+		49: y <= -u1;
+		50: y <= +s1;
+		51: y <= -s1;
+
+		52: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };
+		53: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };
+		54: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };
+		55: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };
+
+		56: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };
+		57: y <= {4{u1[1:0]}};
+		58: y <= {u1, u2} ^ {s1, s2};
+		59: y <= {u1, u2} & {s1, s2};
+
+		60: y <= u1[0] ? u1 : u2;
+		61: y <= u1[0] ? u1 : s2;
+		62: y <= u1[0] ? s1 : u2;
+		63: y <= u1[0] ? s1 : s2;
+	endcase
+end
+
+endmodule
diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v
new file mode 100644
index 00000000..94fd2dfc
--- /dev/null
+++ b/tests/simple/paramods.v
@@ -0,0 +1,37 @@
+
+module test1(a, b, x, y);
+
+input [7:0] a, b;
+output [7:0] x, y;
+
+inc #(.step(3)) inc_a (.in(a), .out(x));
+inc #(.width(4), .step(7)) inc_b (b, y);
+
+endmodule
+
+// -----------------------------------
+
+module test2(a, b, x, y);
+
+input [7:0] a, b;
+output [7:0] x, y;
+
+inc #(5) inc_a (.in(a), .out(x));
+inc #(4, 7) inc_b (b, y);
+
+endmodule
+
+// -----------------------------------
+
+module inc(in, out);
+
+parameter width = 8;
+parameter step = 1;
+
+input [width-1:0] in;
+output [width-1:0] out;
+
+assign out = in + step;
+
+endmodule
+
diff --git a/tests/simple/process.v b/tests/simple/process.v
new file mode 100644
index 00000000..53258664
--- /dev/null
+++ b/tests/simple/process.v
@@ -0,0 +1,65 @@
+
+module uut(clk, arst, a, b, c, d, e, f,  out1);
+
+input clk, arst, a, b, c, d, e, f;
+output reg [3:0] out1;
+
+always @(posedge clk, posedge arst) begin
+	if (arst)
+		out1 = 0;
+	else begin
+		if (a) begin
+			case ({b, c})
+				2'b00:
+					out1 = out1 + 9;
+				2'b01, 2'b10:
+					out1 = out1 + 13;
+			endcase
+			if (d) begin
+				out1 = out1 + 2;
+				out1 = out1 + 1;
+			end
+			case ({e, f})
+				2'b11:
+					out1 = out1 + 8;
+				2'b00:
+					;
+				default:
+					out1 = out1 + 10;
+			endcase
+			out1 = out1 ^ 7;
+		end
+		out1 = out1 + 14;
+	end
+end
+
+endmodule
+
+// -------------------------------------------------------------
+
+// extracted from ../asicworld/code_hdl_models_uart.v
+// (triggered a bug in the proc_mux pass)
+module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);
+
+input reset;
+input txclk;
+input ld_tx_data;
+
+output reg tx_empty;
+output reg [3:0] tx_cnt;
+
+always @ (posedge txclk)
+if (reset) begin
+  tx_empty      <= 1;
+  tx_cnt        <= 0;
+end else begin
+   if (ld_tx_data) begin
+     tx_empty <= 0;
+   end
+   if (!tx_empty) begin
+     tx_cnt <= tx_cnt + 1;
+   end
+end
+
+endmodule
+
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
new file mode 100755
index 00000000..bf27d15f
--- /dev/null
+++ b/tests/simple/run-test.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+make -C ../.. || exit 1
+exec bash ../tools/autotest.sh *.v
diff --git a/tests/simple/subbytes.v b/tests/simple/subbytes.v
new file mode 100644
index 00000000..04269a99
--- /dev/null
+++ b/tests/simple/subbytes.v
@@ -0,0 +1,82 @@
+
+// test taken from systemcaes from iwls2005
+
+module subbytes_00(clk, reset, start_i, decrypt_i, data_i, ready_o, data_o, sbox_data_o, sbox_data_i, sbox_decrypt_o);
+
+input clk;
+input reset;
+input start_i;
+input decrypt_i;
+input [31:0] data_i;
+output ready_o;
+output [31:0] data_o;
+output [7:0] sbox_data_o;
+input [7:0] sbox_data_i;
+output sbox_decrypt_o;
+
+reg ready_o;
+reg [31:0] data_o;
+reg [7:0] sbox_data_o;
+reg sbox_decrypt_o;
+
+reg [1:0] state;
+reg [1:0] next_state;
+reg [31:0] data_reg;
+reg [31:0] next_data_reg;
+reg next_ready_o;
+
+always @(posedge clk or negedge reset)
+begin
+	if (!reset) begin
+		data_reg = 0;
+		state = 0;
+		ready_o = 0;
+	end else begin
+		data_reg = next_data_reg;
+		state = next_state;
+		ready_o = next_ready_o;
+	end
+end
+
+reg [31:0] data_i_var, data_reg_128;
+reg [7:0] data_array [3:0];
+reg [7:0] data_reg_var [3:0];
+
+always @(decrypt_i or start_i or state or data_i or sbox_data_i or data_reg)
+begin
+	data_i_var = data_i;
+
+	data_array[0] = data_i_var[ 31: 24];
+	data_array[1] = data_i_var[ 23: 16];
+	data_array[2] = data_i_var[ 15:  8];
+	data_array[3] = data_i_var[  7:  0];
+
+	data_reg_var[0] = data_reg[ 31: 24];
+	data_reg_var[1] = data_reg[ 23: 16];
+	data_reg_var[2] = data_reg[ 15:  8];
+	data_reg_var[3] = data_reg[  7:  0];
+
+	sbox_decrypt_o = decrypt_i;
+	sbox_data_o = data_array[state];
+	next_state = state;
+	next_data_reg = data_reg;
+
+	next_ready_o = 0;
+	data_o = data_reg;
+
+	if (state) begin
+		if (start_i) begin
+			next_state = 1;
+		end
+	end else begin
+		data_reg_var[state] = sbox_data_i;
+		data_reg_128[ 31: 24] = data_reg_var[0];
+		data_reg_128[ 23: 16] = data_reg_var[1];
+		data_reg_128[ 15:  8] = data_reg_var[2];
+		data_reg_128[  7:  0] = data_reg_var[3];
+		next_data_reg = data_reg_128;
+		next_state = state + 1;
+	end
+end
+
+endmodule
diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
new file mode 100644
index 00000000..3a09cbc3
--- /dev/null
+++ b/tests/simple/task_func.v
@@ -0,0 +1,35 @@
+
+module test01(clk, a, b, c, x, y, z, w);
+
+input clk;
+input [7:0] a, b, c;
+output reg [7:0] x, y, z, w;
+
+function [7:0] sum_shift;
+input [3:0] s1, s2, s3;
+sum_shift = s1 + (s2 << 2) + (s3 << 4);
+endfunction
+
+task reset_w;
+w = 0;
+endtask
+
+task add_to;
+output [7:0] out;
+input [7:0] in;
+out = out + in;
+endtask
+
+always @(posedge clk) begin
+	x = sum_shift(a, b, c);
+	y = sum_shift(a[7:4], b[5:2], c[3:0]);
+	z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3);
+
+	reset_w;
+	add_to(w, x);
+	add_to(w, y);
+	add_to(w, z);
+end
+
+endmodule
+
diff --git a/tests/simple/usb_phy_tetsts.v b/tests/simple/usb_phy_tetsts.v
new file mode 100644
index 00000000..2375183d
--- /dev/null
+++ b/tests/simple/usb_phy_tetsts.v
@@ -0,0 +1,36 @@
+
+// from usb_rx_phy
+module test01(clk, rst, rx_en, fs_ce);
+
+input		clk, rst;
+input		rx_en;
+output reg	fs_ce;
+reg	[1:0]	dpll_next_state;
+reg	[1:0]	dpll_state;
+
+always @(posedge clk)
+	dpll_state <= rst ? 0 : dpll_next_state;
+
+always @*
+   begin
+	fs_ce = 1'b0;
+	case(dpll_state)
+	   2'h0:
+		if(rx_en)	dpll_next_state = 2'h0;
+		else		dpll_next_state = 2'h1;
+	   2'h1:begin
+		fs_ce = 1'b1;
+		if(rx_en)	dpll_next_state = 2'h3;
+		else		dpll_next_state = 2'h2;
+		end
+	   2'h2:
+		if(rx_en)	dpll_next_state = 2'h0;
+		else		dpll_next_state = 2'h3;
+	   2'h3:
+		if(rx_en)	dpll_next_state = 2'h0;
+		else		dpll_next_state = 2'h0;
+	endcase
+   end
+
+endmodule
+
diff --git a/tests/simple/values.v b/tests/simple/values.v
new file mode 100644
index 00000000..9fae4da9
--- /dev/null
+++ b/tests/simple/values.v
@@ -0,0 +1,44 @@
+
+module test_signed(a, b, c, d, y);
+
+input [3:0] a, b, c;
+input signed [3:0] d;
+output reg [7:0] y;
+
+always @* begin
+	if (a && b)
+		y = c;
+	else
+		y = d;
+end
+
+endmodule
+
+module test_const(a, y);
+
+input [3:0] a;
+output reg [28:0] y;
+
+always @*
+	case (a)
+		4'b0000: y = 0;
+		4'b0001: y = 11;
+		4'b0010: y = 222;
+		4'b0011: y = 3456;
+		4'b0100: y = 'b10010010;
+		4'b0101: y = 'h123abc;
+		4'b0110: y = 'o1234567;
+		4'b0111: y = 'd3456789;
+		4'b1000: y = 16'b10010010;
+		4'b1001: y = 16'h123abc;
+		4'b1010: y = 16'o1234567;
+		4'b1011: y = 16'd3456789;
+		4'b1100: y = "foobar";
+		4'b1101: y = "foobarfoobarfoobar";
+		4'b1110: y = 16'h1;
+		4'b1111: y = a;
+		default: y = 'bx;
+	endcase
+
+endmodule
+