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authorClifford Wolf <clifford@clifford.at>2013-12-04 09:24:52 +0100
committerClifford Wolf <clifford@clifford.at>2013-12-04 09:24:52 +0100
commita2d053694b6269bab8871a810142943fac6a3a18 (patch)
tree6e9fcb2b4c04c20c13ba26ef2bb52397eeb3cc34 /tests/simple
parentd1517b7982a4d8be6ceede68577a519952674b4f (diff)
Fix in sincos testbench gen
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/sincos.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple/sincos.v b/tests/simple/sincos.v
index 66156b68..b3124337 100644
--- a/tests/simple/sincos.v
+++ b/tests/simple/sincos.v
@@ -39,7 +39,7 @@ input start;
input clock;
input reset;
-(* gentb_constant="0" *)
+(* gentb_constant = 1'b0 *)
wire reset;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR