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authorClifford Wolf <clifford@clifford.at>2014-01-03 00:22:17 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-03 00:22:17 +0100
commitfb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (patch)
treeea47a664de2af51f09fe43f3040685438f5dd2ec /tests/simple
parent536e20bde159db3ad8c77aeb9001a8dddde884a8 (diff)
Added correct handling of $memwr priority
Diffstat (limited to 'tests/simple')
-rw-r--r--tests/simple/memory.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index aea014a2..eaeee01d 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -1,4 +1,21 @@
+module test00(clk, setA, setB, y);
+
+input clk, setA, setB;
+output y;
+reg mem [1:0];
+
+always @(posedge clk) begin
+ if (setA) mem[0] <= 0; // this is line 9
+ if (setB) mem[0] <= 1; // this is line 10
+end
+
+assign y = mem[0];
+
+endmodule
+
+// ----------------------------------------------------------
+
module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
input clk, wr_en;