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authorRuben Undheim <ruben.undheim@gmail.com>2018-08-30 20:46:20 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2018-08-30 20:46:20 +0200
commit5033b51947a6ef02cb785b5622e993335efa750a (patch)
tree7bed18c526bd94917fa2f08e3df12209863698a1 /tests/sva/basic03.sv
parentfefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff)
New upstream version 0.7+20180830git0b7a184
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+module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
+ always @(posedge clk) begin
+ if (selA) Q <= QA;
+ if (selB) Q <= QB;
+ end
+
+ check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
+ check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
+`ifndef FAIL
+ assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
+`endif
+endmodule