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author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
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committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-08-30 20:46:20 +0200 |
commit | 5033b51947a6ef02cb785b5622e993335efa750a (patch) | |
tree | 7bed18c526bd94917fa2f08e3df12209863698a1 /tests/sva/basic05.vhd | |
parent | fefe0fc0430f4f173a25e674708aa0f4f0854b31 (diff) |
New upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'tests/sva/basic05.vhd')
-rw-r--r-- | tests/sva/basic05.vhd | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/sva/basic05.vhd b/tests/sva/basic05.vhd new file mode 100644 index 00000000..8d42f71e --- /dev/null +++ b/tests/sva/basic05.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity demo is + port ( + clock : in std_logic; + ctrl : in std_logic; + x : out std_logic + ); +end entity; + +architecture rtl of demo is + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal ready : std_logic := '0'; +begin + process (clock) begin + if (rising_edge(clock)) then + read <= not ctrl; + write <= ctrl; + ready <= write; + end if; + end process; + + x <= read xor write xor ready; +end architecture; |