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authorClifford Wolf <clifford@clifford.at>2014-07-28 14:25:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-28 14:25:03 +0200
commit27a872d1e7041be4894bc643a420587ff5894125 (patch)
tree430d0411eaa4c4f6893576e2179d2eee93726def /tests/techmap/.gitignore
parent3c45277ee0f5822181c6058f679de632f834e7d2 (diff)
Added support for "upto" wires to Verilog front- and back-end
Diffstat (limited to 'tests/techmap/.gitignore')
0 files changed, 0 insertions, 0 deletions