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authorClifford Wolf <clifford@clifford.at>2014-02-21 12:06:40 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-21 12:06:40 +0100
commit81b3f52519d388f252405fa7cc7472ca9e51bc49 (patch)
tree26d1faee61bcac2276307c8919b20ca493dfedd2 /tests/techmap/mem_simple_4x1_tb.v
parent79f8944811cba40ca0f3bda98ab951395d24fa0b (diff)
Added tests/techmap/mem_simple_4x1
Diffstat (limited to 'tests/techmap/mem_simple_4x1_tb.v')
-rw-r--r--tests/techmap/mem_simple_4x1_tb.v29
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/techmap/mem_simple_4x1_tb.v b/tests/techmap/mem_simple_4x1_tb.v
new file mode 100644
index 00000000..53262696
--- /dev/null
+++ b/tests/techmap/mem_simple_4x1_tb.v
@@ -0,0 +1,29 @@
+module tb;
+
+reg clk, rst;
+wire [7:0] out;
+wire [4:0] counter;
+
+uut uut (clk, rst, out, counter);
+
+initial begin
+ #5 clk <= 0;
+ repeat (100) #5 clk <= ~clk;
+ #5 $finish;
+end
+
+initial begin
+ rst <= 1;
+ repeat (2) @(posedge clk);
+ rst <= 0;
+end
+
+always @(posedge clk)
+ $display("%d %d %d", rst, out, counter);
+
+initial begin
+ $dumpfile("mem_simple_4x1_tb.vcd");
+ $dumpvars(0, uut);
+end
+
+endmodule