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| author | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
| commit | 288ba9618af9c5ba9db1131955c92d59166d120d (patch) | |
| tree | d65852d388355322a9e7166ba0b0661e24eb220e /tests/tools/autotest.sh | |
| parent | 647c23b7b7e3a72fc64d9b1ad07dacd590865898 (diff) | |
Moved common techlib files to techlibs/common
Diffstat (limited to 'tests/tools/autotest.sh')
| -rwxr-xr-x | tests/tools/autotest.sh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index cb1e3a96..992c8563 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -130,8 +130,8 @@ do "$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v $libs \ - "$toolsdir"/../../techlibs/simlib.v \ - "$toolsdir"/../../techlibs/stdcells_sim.v + "$toolsdir"/../../techlibs/common/simlib.v \ + "$toolsdir"/../../techlibs/common/stdcells_sim.v if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count} test_count=$(( test_count + 1 )) |