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authorClifford Wolf <clifford@clifford.at>2013-11-24 20:44:00 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 20:44:00 +0100
commit1afe6589df136375c4322c9f10812e3b57f1200e (patch)
tree64f7a5a2b49bd5bbf03504f67e136a594bd33a5a /tests/tools
parent8dafecd34d772b1d9ec190b39913b236cdc8fb17 (diff)
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Diffstat (limited to 'tests/tools')
-rwxr-xr-xtests/tools/autotest.sh2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 3d7601eb..5a302bcd 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -139,7 +139,7 @@ do
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
"$toolsdir"/../../techlibs/common/simlib.v \
- "$toolsdir"/../../techlibs/common/stdcells_sim.v
+ "$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
test_count=$(( test_count + 1 ))