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authorClifford Wolf <clifford@clifford.at>2013-11-20 10:51:32 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-20 10:51:32 +0100
commit19dba2561ece488543e1728ba800386943abb77c (patch)
tree1388ba1895b2caba3f832ac0646c1224cfe1e619 /tests
parentd248419fe0ec1f35d2f18b4f4aaf2c9525588fac (diff)
Implemented part/bit select on memory read
Diffstat (limited to 'tests')
-rw-r--r--tests/simple/memory.v41
1 files changed, 41 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index c25bcd92..aea014a2 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -17,3 +17,44 @@ always @(posedge clk)
endmodule
+// ----------------------------------------------------------
+
+module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
+
+input clk, setA, setB;
+input [1:0] addr;
+input [2:0] bit;
+output reg y1, y2;
+output y3, y4;
+
+reg [7:0] mem1 [3:0];
+
+(* mem2reg *)
+reg [7:0] mem2 [3:0];
+
+always @(posedge clk) begin
+ if (setA) begin
+ mem1[0] <= 10;
+ mem1[1] <= 20;
+ mem1[2] <= 30;
+ mem2[0] <= 17;
+ mem2[1] <= 27;
+ mem2[2] <= 37;
+ end
+ if (setB) begin
+ mem1[0] <= 1;
+ mem1[1] <= 2;
+ mem1[2] <= 3;
+ mem2[0] <= 71;
+ mem2[1] <= 72;
+ mem2[2] <= 73;
+ end
+ y1 <= mem1[addr][bit];
+ y2 <= mem2[addr][bit];
+end
+
+assign y3 = mem1[addr][bit];
+assign y4 = mem2[addr][bit];
+
+endmodule
+